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Commit 569c7edf authored by Tapas Dey's avatar Tapas Dey Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add NFC device node for SM6125



Device node changes required on SM6125 describing
the GPIO configuration for Nfc controller chip.

Modified corresponding Nfc device node for
QRD and IDP platform.

Change-Id: I8e1bca110f98e030d1cd60a429dbe45aa06c2f3c
Signed-off-by: default avatarTapas Dey <tdey@codeaurora.org>
parent a74cb474
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+21 −0
Original line number Diff line number Diff line
@@ -70,6 +70,27 @@
	};
};

&qupv3_se1_i2c {
	status = "ok";
	qcom,clk-freq-out = <1000000>;
	nq@28 {
		compatible = "qcom,nq-nci";
		reg = <0x28>;
		qcom,nq-irq = <&tlmm 85 0x00>;
		qcom,nq-ven = <&tlmm 83 0x00>;
		qcom,nq-firm = <&tlmm 84 0x00>;
		qcom,nq-clkreq = <&tlmm 95 0x00>;
		interrupt-parent = <&tlmm>;
		interrupts = <85 0>;
		interrupt-names = "nfc_irq";
		pinctrl-names = "nfc_active", "nfc_suspend";
		pinctrl-0 = <&nfc_int_active &nfc_enable_active
				&nfc_clk_req_active>;
		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
				&nfc_clk_req_suspend>;
	};
};

&sdhc_1 {
	vdd-supply = <&pm6125_l24>;
	qcom,vdd-voltage-level = <2950000 2950000>;
+92 −0
Original line number Diff line number Diff line
@@ -81,6 +81,98 @@
			};
		};

		nfc {
			nfc_int_active: nfc_int_active {
				/* active state */
				mux {
					/* GPIO 85 NFC Read Interrupt */
					pins = "gpio85";
					function = "gpio";
				};

				config {
					pins = "gpio85";
					drive-strength = <2>; /* 2 MA */
					bias-pull-up;
				};
			};

			nfc_int_suspend: nfc_int_suspend {
				/* sleep state */
				mux {
					/* GPIO 85 NFC Read Interrupt */
					pins = "gpio85";
					function = "gpio";
				};

				config {
					pins = "gpio85";
					drive-strength = <2>; /* 2 MA */
					bias-pull-up;
				};
			};

			nfc_enable_active: nfc_enable_active {
				/* active state */
				mux {
					/* 83: Enable 84: Firmware */
					pins = "gpio83", "gpio84";
					function = "gpio";
				};

				config {
					pins = "gpio83", "gpio84";
					drive-strength = <2>; /* 2 MA */
					bias-pull-up;
				};
			};

			nfc_enable_suspend: nfc_enable_suspend {
				/* sleep state */
				mux {
					/* 83: Enable 84: Firmware */
					pins = "gpio83", "gpio84";
					function = "gpio";
				};

				config {
					pins = "gpio83", "gpio84";
					drive-strength = <2>; /* 2 MA */
					bias-disable;
				};
			};

			nfc_clk_req_active: nfc_clk_req_active {
				/* active state */
				mux {
					/* GPIO 95: NFC CLOCK REQUEST */
					pins = "gpio95";
					function = "gpio";
				};

				config {
					pins = "gpio95";
					drive-strength = <2>; /* 2 MA */
					bias-pull-up;
				};
			};

			nfc_clk_req_suspend: nfc_clk_req_suspend {
				/* sleep state */
				mux {
					/* GPIO 95: NFC CLOCK REQUEST */
					pins = "gpio95";
					function = "gpio";
				};

				config {
					pins = "gpio95";
					drive-strength = <2>; /* 2 MA */
					bias-disable;
				};
			};
		};

		/* SE 2 pin mappings */
		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
			qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+21 −0
Original line number Diff line number Diff line
@@ -83,6 +83,27 @@
	};
};

&qupv3_se1_i2c {
	status = "ok";
	qcom,clk-freq-out = <1000000>;
	nq@28 {
		compatible = "qcom,nq-nci";
		reg = <0x28>;
		qcom,nq-irq = <&tlmm 85 0x00>;
		qcom,nq-ven = <&tlmm 83 0x00>;
		qcom,nq-firm = <&tlmm 84 0x00>;
		qcom,nq-clkreq = <&tlmm 95 0x00>;
		interrupt-parent = <&tlmm>;
		interrupts = <85 0>;
		interrupt-names = "nfc_irq";
		pinctrl-names = "nfc_active", "nfc_suspend";
		pinctrl-0 = <&nfc_int_active &nfc_enable_active
				&nfc_clk_req_active>;
		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
				&nfc_clk_req_suspend>;
	};
};

&sdhc_1 {
	vdd-supply = <&pm6125_l24>;
	qcom,vdd-voltage-level = <2950000 2950000>;