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Commit 5685e38b authored by David Collins's avatar David Collins Committed by Gerrit - the friendly Code Review server
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clk: qcom: add VIDEOCC clock driver for SDM855 



Add the VIDEOCC clock definitions and driver support for SDM855.

Change-Id: I5b91b3526f2928795a02b96c6c768427b66382f0
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent 903bbcb1

Documentation/devicetree/bindings/clock/qcom,videocc.txt

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Qualcomm Technologies, Inc. Video Clock & Reset Controller Bindings



Required properties:

- compatible: shall contain "qcom,videocc-sdm855".

- reg: shall contain base register location and length.

- reg-names: names of registers listed in the same order as in the reg property.

- #clock-cells: shall contain 1.

- #reset-cells: shall contain 1.



Optional properties:

- vdd_<rail>-supply: the logic rail supply.



Example:

	qcom,videocc@ab00000 {

		compatible = "qcom,videocc-sdm855";

		reg = <0xab00000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm855l_s5_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

drivers/clk/qcom/Kconfig

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@@ -222,3 +222,12 @@ config MSM_NPUCC_SDM855 
          Support for the NPU clock controller on Qualcomm Technologies, Inc

          Support for the NPU clock controller on Qualcomm Technologies, Inc

	  SDM855 devices.

	  SDM855 devices.

	  Say Y if you want to enable use of the Network Processing Unit.

	  Say Y if you want to enable use of the Network Processing Unit.



config MSM_VIDEOCC_SDM855

	tristate "SDM855 Video Clock Controller"

	depends on COMMON_CLK_QCOM

	help

	  Support for the video clock controller on Qualcomm Technologies, Inc.

	  SDM855 devices.

	  Say Y if you want to support video devices and functionality such as

	  video encode/decode.

drivers/clk/qcom/Makefile

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@@ -36,5 +36,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o 
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o

obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o

obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o

obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o

obj-$(CONFIG_MSM_NPUCC_SDM855) += npucc-sdm855.o

obj-$(CONFIG_MSM_NPUCC_SDM855) += npucc-sdm855.o

obj-$(CONFIG_MSM_VIDEOCC_SDM855) += videocc-sdm855.o

obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o

obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o

obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o

drivers/clk/qcom/videocc-sdm855.c

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/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#define pr_fmt(fmt) "clk: %s: " fmt, __func__



#include <linux/kernel.h>

#include <linux/bitops.h>

#include <linux/err.h>

#include <linux/platform_device.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/regmap.h>

#include <linux/reset-controller.h>



#include <dt-bindings/clock/qcom,videocc-sdm855.h>



#include "common.h"

#include "clk-regmap.h"

#include "clk-pll.h"

#include "clk-rcg.h"

#include "clk-branch.h"

#include "reset.h"

#include "clk-alpha-pll.h"

#include "vdd-level.h"



#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }



static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);



enum {

	P_BI_TCXO,

	P_CORE_BI_PLL_TEST_SE,

	P_VIDEO_PLL0_OUT_EVEN,

	P_VIDEO_PLL0_OUT_MAIN,

	P_VIDEO_PLL0_OUT_ODD,

};



static const struct parent_map video_cc_parent_map_0[] = {

	{ P_BI_TCXO, 0 },

	{ P_VIDEO_PLL0_OUT_MAIN, 1 },

	{ P_VIDEO_PLL0_OUT_EVEN, 2 },

	{ P_VIDEO_PLL0_OUT_ODD, 3 },

	{ P_CORE_BI_PLL_TEST_SE, 7 },

};



static const char * const video_cc_parent_names_0[] = {

	"bi_tcxo",

	"video_pll0",

	"video_pll0_out_even",

	"video_pll0_out_odd",

	"core_bi_pll_test_se",

};



static struct pll_vco trion_vco[] = {

	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config video_pll0_config = {

	.l = 0x14,

	.alpha = 0xd555,

};



static struct clk_alpha_pll video_pll0 = {

	.offset = 0x42c,

	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "video_pll0",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_trion_pll_ops,

			.vdd_class = &vdd_mm,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};



static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {

	F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),

	F(225000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),

	F(300000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),

	F(365000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),

	F(444000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),

	F(533000000, P_VIDEO_PLL0_OUT_MAIN, 3, 0, 0),

	{ }

};



static struct clk_rcg2 video_cc_iris_clk_src = {

	.cmd_rcgr = 0x7f0,

	.mnd_width = 0,

	.hid_width = 5,

	.parent_map = video_cc_parent_map_0,

	.freq_tbl = ftbl_video_cc_iris_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "video_cc_iris_clk_src",

		.parent_names = video_cc_parent_names_0,

		.num_parents = 5,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 200000000,

			[VDD_LOWER] = 225000000,

			[VDD_LOW] = 300000000,

			[VDD_LOW_L1] = 365000000,

			[VDD_NOMINAL] = 444000000,

			[VDD_HIGH] = 533000000},

	},

};



static struct clk_branch video_cc_iris_ahb_clk = {

	.halt_reg = 0x8f4,

	.halt_check = BRANCH_VOTED,

	.clkr = {

		.enable_reg = 0x8f4,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_iris_ahb_clk",

			.parent_names = (const char *[]){

				"video_cc_iris_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_mvs0_core_clk = {

	.halt_reg = 0x890,

	.halt_check = BRANCH_VOTED,

	.clkr = {

		.enable_reg = 0x890,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs0_core_clk",

			.parent_names = (const char *[]){

				"video_cc_iris_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_mvs1_core_clk = {

	.halt_reg = 0x8d0,

	.halt_check = BRANCH_VOTED,

	.clkr = {

		.enable_reg = 0x8d0,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvs1_core_clk",

			.parent_names = (const char *[]){

				"video_cc_iris_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_mvsc_core_clk = {

	.halt_reg = 0x850,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x850,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_mvsc_core_clk",

			.parent_names = (const char *[]){

				"video_cc_iris_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch video_cc_xo_clk = {

	.halt_reg = 0x984,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x984,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "video_cc_xo_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_regmap *video_cc_sdm855_clocks[] = {

	[VIDEO_CC_IRIS_AHB_CLK] = &video_cc_iris_ahb_clk.clkr,

	[VIDEO_CC_IRIS_CLK_SRC] = &video_cc_iris_clk_src.clkr,

	[VIDEO_CC_MVS0_CORE_CLK] = &video_cc_mvs0_core_clk.clkr,

	[VIDEO_CC_MVS1_CORE_CLK] = &video_cc_mvs1_core_clk.clkr,

	[VIDEO_CC_MVSC_CORE_CLK] = &video_cc_mvsc_core_clk.clkr,

	[VIDEO_CC_XO_CLK] = &video_cc_xo_clk.clkr,

	[VIDEO_PLL0] = &video_pll0.clkr,

};



static const struct regmap_config video_cc_sdm855_regmap_config = {

	.reg_bits	= 32,

	.reg_stride	= 4,

	.val_bits	= 32,

	.max_register	= 0xb94,

	.fast_io	= true,

};



static const struct qcom_cc_desc video_cc_sdm855_desc = {

	.config = &video_cc_sdm855_regmap_config,

	.clks = video_cc_sdm855_clocks,

	.num_clks = ARRAY_SIZE(video_cc_sdm855_clocks),

};



static const struct of_device_id video_cc_sdm855_match_table[] = {

	{ .compatible = "qcom,videocc-sdm855" },

	{ }

};

MODULE_DEVICE_TABLE(of, video_cc_sdm855_match_table);



static int video_cc_sdm855_probe(struct platform_device *pdev)

{

	struct regmap *regmap;

	int ret;



	regmap = qcom_cc_map(pdev, &video_cc_sdm855_desc);

	if (IS_ERR(regmap)) {

		pr_err("Failed to map the Video CC registers\n");

		return PTR_ERR(regmap);

	}



	vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");

	if (IS_ERR(vdd_mm.regulator[0])) {

		if (!(PTR_ERR(vdd_mm.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");

		return PTR_ERR(vdd_mm.regulator[0]);

	}



	clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);



	ret = qcom_cc_really_probe(pdev, &video_cc_sdm855_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register Video CC clocks\n");

		return ret;

	}



	dev_info(&pdev->dev, "Registered Video CC clocks\n");



	return ret;

}



static struct platform_driver video_cc_sdm855_driver = {

	.probe		= video_cc_sdm855_probe,

	.driver		= {

		.name	= "video_cc-sdm855",

		.of_match_table = video_cc_sdm855_match_table,

	},

};



static int __init video_cc_sdm855_init(void)

{

	return platform_driver_register(&video_cc_sdm855_driver);

}

subsys_initcall(video_cc_sdm855_init);



static void __exit video_cc_sdm855_exit(void)

{

	platform_driver_unregister(&video_cc_sdm855_driver);

}

module_exit(video_cc_sdm855_exit);



MODULE_DESCRIPTION("QTI VIDEO_CC SDM855 Driver");

MODULE_LICENSE("GPL v2");

MODULE_ALIAS("platform:video_cc-sdm855");

include/dt-bindings/clock/qcom,videocc-sdm855.h

+2 −6
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@@ -19,11 +19,7 @@ 
#define VIDEO_CC_MVS0_CORE_CLK					2

#define VIDEO_CC_MVS0_CORE_CLK					2

#define VIDEO_CC_MVS1_CORE_CLK					3

#define VIDEO_CC_MVS1_CORE_CLK					3

#define VIDEO_CC_MVSC_CORE_CLK					4

#define VIDEO_CC_MVSC_CORE_CLK					4

#define VIDEO_PLL0						5

#define VIDEO_CC_XO_CLK						5



#define VIDEO_PLL0						6

#define VIDEO_CC_INTERFACE_BCR					0

#define VIDEO_CC_MVS0_BCR					1

#define VIDEO_CC_MVS1_BCR					2

#define VIDEO_CC_MVSC_BCR					3





#endif
 
#endif