Loading Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt 0 → 100644 +163 −0 Original line number Diff line number Diff line Message unit node: For SRIO controllers that implement the message unit as part of the controller this node is required. For devices with RMAN this node should NOT exist. The node is composed of three types of sub-nodes ("fsl-srio-msg-unit", "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit"). See srio.txt for more details about generic SRIO controller details. - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu". The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - fsl,liodn Usage: optional-but-recommended (for devices with PAMU) Value type: <prop-encoded-array> Definition: The logical I/O device number for the PAMU (IOMMU) to be correctly configured for SRIO accesses. The property should not exist on devices that do not support PAMU. The LIODN value is associated with all RMU transactions (msg-unit, doorbell, port-write). Sub-Nodes for RMU: The RMU node is composed of multiple sub-nodes that correspond to the actual sub-controllers in the RMU. The manual for a given SoC will detail which and how many of these sub-controllers are implemented. Message Unit: - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit". The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A pair of IRQs are specified in this property. The first element is associated with the transmit (TX) interrupt and the second element is associated with the receive (RX) interrupt. Doorbell Unit: - compatible Usage: required Value type: <string> Definition: Must include: "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit" The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A pair of IRQs are specified in this property. The first element is associated with the transmit (TX) interrupt and the second element is associated with the receive (RX) interrupt. Port-Write Unit: - compatible Usage: required Value type: <string> Definition: Must include: "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit" The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A single IRQ that handles port-write conditions is specified by this property. (Typically shared with error). Note: All other standard properties (see the ePAPR) are allowed but are optional. Example: rmu: rmu@d3000 { compatible = "fsl,srio-rmu"; reg = <0xd3000 0x400>; ranges = <0x0 0xd3000 0x400>; fsl,liodn = <0xc8>; message-unit@0 { compatible = "fsl,srio-msg-unit"; reg = <0x0 0x100>; interrupts = < 60 2 0 0 /* msg1_tx_irq */ 61 2 0 0>;/* msg1_rx_irq */ }; message-unit@100 { compatible = "fsl,srio-msg-unit"; reg = <0x100 0x100>; interrupts = < 62 2 0 0 /* msg2_tx_irq */ 63 2 0 0>;/* msg2_rx_irq */ }; doorbell-unit@400 { compatible = "fsl,srio-dbell-unit"; reg = <0x400 0x80>; interrupts = < 56 2 0 0 /* bell_outb_irq */ 57 2 0 0>;/* bell_inb_irq */ }; port-write-unit@4e0 { compatible = "fsl,srio-port-write-unit"; reg = <0x4e0 0x20>; interrupts = <16 2 1 11>; }; }; Documentation/devicetree/bindings/powerpc/fsl/srio.txt 0 → 100644 +103 −0 Original line number Diff line number Diff line * Freescale Serial RapidIO (SRIO) Controller RapidIO port node: Properties: - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio" for IP blocks with IP Block Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major version in IP Block Revision Register and Y is Minor version. If this compatiable is provided it should be ordered before "fsl,srio". - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers. The size should be set to 0x11000. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A single IRQ that handles error conditions is specified by this property. (Typically shared with port-write). - fsl,srio-rmu-handle: Usage: required if rmu node is defined Value type: <phandle> Definition: A single <phandle> value that points to the RMU. (See srio-rmu.txt for more details on RMU node binding) Port Child Nodes: There should a port child node for each port that exists in the controller. The ports are numbered starting at one (1) and should have the following properties: - cell-index Usage: required Value type: <u32> Definition: A standard property. Matches the port id. - ranges Usage: required if local access windows preset Value type: <prop-encoded-array> Definition: A standard property. Utilized to describe the memory mapped IO space utilized by the controller. This corresponds to the setting of the local access windows that are targeted to this SRIO port. - fsl,liodn Usage: optional-but-recommended (for devices with PAMU) Value type: <prop-encoded-array> Definition: The logical I/O device number for the PAMU (IOMMU) to be correctly configured for SRIO accesses. The property should not exist on devices that do not support PAMU. For HW (ie, the P4080) that only supports a LIODN for both memory and maintenance transactions then a single LIODN is represented in the property for both transactions. For HW (ie, the P304x/P5020, etc) that supports an LIODN for memory transactions and a unique LIODN for maintenance transactions then a pair of LIODNs are represented in the property. Within the pair, the first element represents the LIODN associated with memory transactions and the second element represents the LIODN associated with maintenance transactions for the port. Note: All other standard properties (see ePAPR) are allowed but are optional. Example: rapidio: rapidio@ffe0c0000 { #address-cells = <2>; #size-cells = <2>; reg = <0xf 0xfe0c0000 0 0x11000>; compatible = "fsl,srio"; interrupts = <16 2 1 11>; /* err_irq */ fsl,srio-rmu-handle = <&rmu>; ranges; port1 { cell-index = <1>; #address-cells = <2>; #size-cells = <2>; fsl,liodn = <34>; ranges = <0 0 0xc 0x20000000 0 0x10000000>; }; port2 { cell-index = <2>; #address-cells = <2>; #size-cells = <2>; fsl,liodn = <48>; ranges = <0 0 0xc 0x30000000 0 0x10000000>; }; }; arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 0 → 100644 +248 −0 Original line number Diff line number Diff line /* * MPC8536 Silicon/SoC Device Tree Source (post include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &lbc { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus"; interrupts = <19 2 0 0>; }; /* controller at 0x8000 */ &pci0 { compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupts = <24 0x2 0 0>; bus-range = <0 0xff>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; }; /* controller at 0x9000 */ &pci1 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <25 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <25 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 >; }; }; /* controller at 0xa000 */ &pci2 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <26 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <26 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 >; }; }; /* controller at 0xb000 */ &pci3 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <27 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <27 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 >; }; }; &soc { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8536-immr", "simple-bus"; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <12>; }; ecm@1000 { compatible = "fsl,mpc8536-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2 0 0>; }; memory-controller@2000 { compatible = "fsl,mpc8536-memory-controller"; reg = <0x2000 0x1000>; interrupts = <18 2 0 0>; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" /include/ "pq3-espi-0.dtsi" spi@7000 { fsl,espi-num-chipselects = <4>; }; /include/ "pq3-gpio-0.dtsi" /* mark compat w/8572 to get some erratum treatment */ gpio-controller@f000 { compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio"; }; sata@18000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x18000 0x1000>; cell-index = <1>; interrupts = <74 0x2 0 0>; }; sata@19000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x19000 0x1000>; cell-index = <2>; interrupts = <41 0x2 0 0>; }; L2: l2-cache-controller@20000 { compatible = "fsl,mpc8536-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x80000>; // L2, 512K interrupts = <16 2 0 0>; }; /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" usb@22000 { compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; reg = <0x22000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <28 0x2 0 0>; }; usb@23000 { compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; reg = <0x23000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <46 0x2 0 0>; }; ptp_clock@24e00 { interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>; }; /include/ "pq3-etsec1-2.dtsi" ethernet@26000 { cell-index = <1>; }; usb@2b000 { compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr"; reg = <0x2b000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <60 0x2 0 0>; }; /include/ "pq3-esdhc-0.dtsi" /include/ "pq3-sec3.0-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" global-utilities@e0000 { compatible = "fsl,mpc8536-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi 0 → 100644 +63 −0 Original line number Diff line number Diff line /* * MPC8536 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; / { compatible = "fsl,MPC8536"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { serial0 = &serial0; serial1 = &serial1; ethernet0 = &enet0; ethernet1 = &enet2; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; pci3 = &pci3; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8536@0 { device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; }; }; }; arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi 0 → 100644 +191 −0 Original line number Diff line number Diff line /* * MPC8544 Silicon/SoC Device Tree Source (post include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &lbc { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus"; interrupts = <19 2 0 0>; }; /* controller at 0x8000 */ &pci0 { compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupts = <24 0x2 0 0>; bus-range = <0 0xff>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; }; /* controller at 0x9000 */ &pci1 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <25 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <25 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 >; }; }; /* controller at 0xa000 */ &pci2 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <26 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <26 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 >; }; }; /* controller at 0xb000 */ &pci3 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <27 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <27 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 >; }; }; &soc { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8544-immr", "simple-bus"; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; ecm@1000 { compatible = "fsl,mpc8544-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2 0 0>; }; memory-controller@2000 { compatible = "fsl,mpc8544-memory-controller"; reg = <0x2000 0x1000>; interrupts = <18 2 0 0>; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" L2: l2-cache-controller@20000 { compatible = "fsl,mpc8544-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x40000>; // L2, 256K interrupts = <16 2 0 0>; }; /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-2.dtsi" ethernet@26000 { cell-index = <1>; }; /include/ "pq3-sec2.1-0.dtsi" /include/ "pq3-mpic.dtsi" global-utilities@e0000 { compatible = "fsl,mpc8544-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; }; Loading
Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt 0 → 100644 +163 −0 Original line number Diff line number Diff line Message unit node: For SRIO controllers that implement the message unit as part of the controller this node is required. For devices with RMAN this node should NOT exist. The node is composed of three types of sub-nodes ("fsl-srio-msg-unit", "fsl-srio-dbell-unit" and "fsl-srio-port-write-unit"). See srio.txt for more details about generic SRIO controller details. - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu". The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - fsl,liodn Usage: optional-but-recommended (for devices with PAMU) Value type: <prop-encoded-array> Definition: The logical I/O device number for the PAMU (IOMMU) to be correctly configured for SRIO accesses. The property should not exist on devices that do not support PAMU. The LIODN value is associated with all RMU transactions (msg-unit, doorbell, port-write). Sub-Nodes for RMU: The RMU node is composed of multiple sub-nodes that correspond to the actual sub-controllers in the RMU. The manual for a given SoC will detail which and how many of these sub-controllers are implemented. Message Unit: - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit". The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A pair of IRQs are specified in this property. The first element is associated with the transmit (TX) interrupt and the second element is associated with the receive (RX) interrupt. Doorbell Unit: - compatible Usage: required Value type: <string> Definition: Must include: "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit" The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A pair of IRQs are specified in this property. The first element is associated with the transmit (TX) interrupt and the second element is associated with the receive (RX) interrupt. Port-Write Unit: - compatible Usage: required Value type: <string> Definition: Must include: "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit" The version X.Y should match the general SRIO controller's IP Block revision register's Major(X) and Minor (Y) value. - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers for message units and doorbell units. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A single IRQ that handles port-write conditions is specified by this property. (Typically shared with error). Note: All other standard properties (see the ePAPR) are allowed but are optional. Example: rmu: rmu@d3000 { compatible = "fsl,srio-rmu"; reg = <0xd3000 0x400>; ranges = <0x0 0xd3000 0x400>; fsl,liodn = <0xc8>; message-unit@0 { compatible = "fsl,srio-msg-unit"; reg = <0x0 0x100>; interrupts = < 60 2 0 0 /* msg1_tx_irq */ 61 2 0 0>;/* msg1_rx_irq */ }; message-unit@100 { compatible = "fsl,srio-msg-unit"; reg = <0x100 0x100>; interrupts = < 62 2 0 0 /* msg2_tx_irq */ 63 2 0 0>;/* msg2_rx_irq */ }; doorbell-unit@400 { compatible = "fsl,srio-dbell-unit"; reg = <0x400 0x80>; interrupts = < 56 2 0 0 /* bell_outb_irq */ 57 2 0 0>;/* bell_inb_irq */ }; port-write-unit@4e0 { compatible = "fsl,srio-port-write-unit"; reg = <0x4e0 0x20>; interrupts = <16 2 1 11>; }; };
Documentation/devicetree/bindings/powerpc/fsl/srio.txt 0 → 100644 +103 −0 Original line number Diff line number Diff line * Freescale Serial RapidIO (SRIO) Controller RapidIO port node: Properties: - compatible Usage: required Value type: <string> Definition: Must include "fsl,srio" for IP blocks with IP Block Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major version in IP Block Revision Register and Y is Minor version. If this compatiable is provided it should be ordered before "fsl,srio". - reg Usage: required Value type: <prop-encoded-array> Definition: A standard property. Specifies the physical address and length of the SRIO configuration registers. The size should be set to 0x11000. - interrupts Usage: required Value type: <prop_encoded-array> Definition: Specifies the interrupts generated by this device. The value of the interrupts property consists of one interrupt specifier. The format of the specifier is defined by the binding document describing the node's interrupt parent. A single IRQ that handles error conditions is specified by this property. (Typically shared with port-write). - fsl,srio-rmu-handle: Usage: required if rmu node is defined Value type: <phandle> Definition: A single <phandle> value that points to the RMU. (See srio-rmu.txt for more details on RMU node binding) Port Child Nodes: There should a port child node for each port that exists in the controller. The ports are numbered starting at one (1) and should have the following properties: - cell-index Usage: required Value type: <u32> Definition: A standard property. Matches the port id. - ranges Usage: required if local access windows preset Value type: <prop-encoded-array> Definition: A standard property. Utilized to describe the memory mapped IO space utilized by the controller. This corresponds to the setting of the local access windows that are targeted to this SRIO port. - fsl,liodn Usage: optional-but-recommended (for devices with PAMU) Value type: <prop-encoded-array> Definition: The logical I/O device number for the PAMU (IOMMU) to be correctly configured for SRIO accesses. The property should not exist on devices that do not support PAMU. For HW (ie, the P4080) that only supports a LIODN for both memory and maintenance transactions then a single LIODN is represented in the property for both transactions. For HW (ie, the P304x/P5020, etc) that supports an LIODN for memory transactions and a unique LIODN for maintenance transactions then a pair of LIODNs are represented in the property. Within the pair, the first element represents the LIODN associated with memory transactions and the second element represents the LIODN associated with maintenance transactions for the port. Note: All other standard properties (see ePAPR) are allowed but are optional. Example: rapidio: rapidio@ffe0c0000 { #address-cells = <2>; #size-cells = <2>; reg = <0xf 0xfe0c0000 0 0x11000>; compatible = "fsl,srio"; interrupts = <16 2 1 11>; /* err_irq */ fsl,srio-rmu-handle = <&rmu>; ranges; port1 { cell-index = <1>; #address-cells = <2>; #size-cells = <2>; fsl,liodn = <34>; ranges = <0 0 0xc 0x20000000 0 0x10000000>; }; port2 { cell-index = <2>; #address-cells = <2>; #size-cells = <2>; fsl,liodn = <48>; ranges = <0 0 0xc 0x30000000 0 0x10000000>; }; };
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi 0 → 100644 +248 −0 Original line number Diff line number Diff line /* * MPC8536 Silicon/SoC Device Tree Source (post include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &lbc { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus"; interrupts = <19 2 0 0>; }; /* controller at 0x8000 */ &pci0 { compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupts = <24 0x2 0 0>; bus-range = <0 0xff>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; }; /* controller at 0x9000 */ &pci1 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <25 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <25 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 >; }; }; /* controller at 0xa000 */ &pci2 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <26 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <26 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 >; }; }; /* controller at 0xb000 */ &pci3 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <27 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <27 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 >; }; }; &soc { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8536-immr", "simple-bus"; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <12>; }; ecm@1000 { compatible = "fsl,mpc8536-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2 0 0>; }; memory-controller@2000 { compatible = "fsl,mpc8536-memory-controller"; reg = <0x2000 0x1000>; interrupts = <18 2 0 0>; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" /include/ "pq3-espi-0.dtsi" spi@7000 { fsl,espi-num-chipselects = <4>; }; /include/ "pq3-gpio-0.dtsi" /* mark compat w/8572 to get some erratum treatment */ gpio-controller@f000 { compatible = "fsl,mpc8572-gpio", "fsl,pq3-gpio"; }; sata@18000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x18000 0x1000>; cell-index = <1>; interrupts = <74 0x2 0 0>; }; sata@19000 { compatible = "fsl,mpc8536-sata", "fsl,pq-sata"; reg = <0x19000 0x1000>; cell-index = <2>; interrupts = <41 0x2 0 0>; }; L2: l2-cache-controller@20000 { compatible = "fsl,mpc8536-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x80000>; // L2, 512K interrupts = <16 2 0 0>; }; /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" usb@22000 { compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; reg = <0x22000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <28 0x2 0 0>; }; usb@23000 { compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; reg = <0x23000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <46 0x2 0 0>; }; ptp_clock@24e00 { interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>; }; /include/ "pq3-etsec1-2.dtsi" ethernet@26000 { cell-index = <1>; }; usb@2b000 { compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr"; reg = <0x2b000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <60 0x2 0 0>; }; /include/ "pq3-esdhc-0.dtsi" /include/ "pq3-sec3.0-0.dtsi" /include/ "pq3-mpic.dtsi" /include/ "pq3-mpic-timer-B.dtsi" global-utilities@e0000 { compatible = "fsl,mpc8536-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; };
arch/powerpc/boot/dts/fsl/mpc8536si-pre.dtsi 0 → 100644 +63 −0 Original line number Diff line number Diff line /* * MPC8536 Silicon/SoC Device Tree Source (pre include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; / { compatible = "fsl,MPC8536"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; aliases { serial0 = &serial0; serial1 = &serial1; ethernet0 = &enet0; ethernet1 = &enet2; pci0 = &pci0; pci1 = &pci1; pci2 = &pci2; pci3 = &pci3; }; cpus { #address-cells = <1>; #size-cells = <0>; PowerPC,8536@0 { device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; }; }; };
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi 0 → 100644 +191 −0 Original line number Diff line number Diff line /* * MPC8544 Silicon/SoC Device Tree Source (post include) * * Copyright 2011 Freescale Semiconductor Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * Neither the name of Freescale Semiconductor nor the * names of its contributors may be used to endorse or promote products * derived from this software without specific prior written permission. * * * ALTERNATIVELY, this software may be distributed under the terms of the * GNU General Public License ("GPL") as published by the Free Software * Foundation, either version 2 of that License or (at your option) any * later version. * * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ &lbc { #address-cells = <2>; #size-cells = <1>; compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus"; interrupts = <19 2 0 0>; }; /* controller at 0x8000 */ &pci0 { compatible = "fsl,mpc8540-pci"; device_type = "pci"; interrupts = <24 0x2 0 0>; bus-range = <0 0xff>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; }; /* controller at 0x9000 */ &pci1 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <25 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <25 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 >; }; }; /* controller at 0xa000 */ &pci2 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <26 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <26 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 >; }; }; /* controller at 0xb000 */ &pci3 { compatible = "fsl,mpc8548-pcie"; device_type = "pci"; #size-cells = <2>; #address-cells = <3>; bus-range = <0 255>; clock-frequency = <33333333>; interrupts = <27 2 0 0>; pcie@0 { reg = <0 0 0 0 0>; #interrupt-cells = <1>; #size-cells = <2>; #address-cells = <3>; device_type = "pci"; interrupts = <27 2 0 0>; interrupt-map-mask = <0xf800 0 0 7>; interrupt-map = < /* IDSEL 0x0 */ 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 >; }; }; &soc { #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "fsl,mpc8544-immr", "simple-bus"; bus-frequency = <0>; // Filled out by uboot. ecm-law@0 { compatible = "fsl,ecm-law"; reg = <0x0 0x1000>; fsl,num-laws = <10>; }; ecm@1000 { compatible = "fsl,mpc8544-ecm", "fsl,ecm"; reg = <0x1000 0x1000>; interrupts = <17 2 0 0>; }; memory-controller@2000 { compatible = "fsl,mpc8544-memory-controller"; reg = <0x2000 0x1000>; interrupts = <18 2 0 0>; }; /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" L2: l2-cache-controller@20000 { compatible = "fsl,mpc8544-l2-cache-controller"; reg = <0x20000 0x1000>; cache-line-size = <32>; // 32 bytes cache-size = <0x40000>; // L2, 256K interrupts = <16 2 0 0>; }; /include/ "pq3-dma-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-2.dtsi" ethernet@26000 { cell-index = <1>; }; /include/ "pq3-sec2.1-0.dtsi" /include/ "pq3-mpic.dtsi" global-utilities@e0000 { compatible = "fsl,mpc8544-guts"; reg = <0xe0000 0x1000>; fsl,has-rstcr; }; };
