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Commit 55a6cf5d authored by Mike Rapoport's avatar Mike Rapoport Committed by Greg Kroah-Hartman
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staging: sm750fb: remove unused calcPllValue2 function 



The calcPllValue2 function is never called and therefore it can be
removed.

Signed-off-by: default avatarMike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent fb6f37a8

drivers/staging/sm750fb/ddk750_chip.c

+0 −100
Original line number Diff line number Diff line
@@ -430,106 +430,6 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) 
	return ret;

}



unsigned int calcPllValue2(

unsigned int ulRequestClk, /* Required pixel clock in Hz unit */

pll_value_t *pPLL           /* Structure to hold the value to be set in PLL */

)

{

	unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;

	unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */

	unsigned int ret;

    /* Init PLL structure to know states */

	pPLL->M = 0;

	pPLL->N = 0;

	pPLL->OD = 0;

	pPLL->POD = 0;



    /* Sanity check: None at the moment */



    /* Convert everything in Khz range in order to avoid calculation overflow */

	pPLL->inputFreq /= 1000;

	ulRequestClk /= 1000;



#ifndef VALIDATION_CHIP

    /* The maximum of post divider is 8. */

	for (POD = 0; POD <= 3; POD++)

#endif

		{



#ifndef VALIDATION_CHIP

	/* MXCLK_PLL does not have post divider. */

	if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))

		break;

#endif



	/* Work out 2 to the power of POD */

	podPower = 1 << POD;



	/* OD has only 2 bits [15:14] and its value must between 0 to 3 */

	for (OD = 0; OD <= 3; OD++) {

		/* Work out 2 to the power of OD */

		odPower = 1 << OD;



#ifdef VALIDATION_CHIP

	if (odPower > 4)

		podPower = 4;

	else

		podPower = odPower;

#endif



		/* N has 4 bits [11:8] and its value must between 2 and 15.

		The N == 1 will behave differently --> Result is not correct. */

	for (N = 2; N <= 15; N++) {

		/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)

		In the following steps, we try to work out a best M value given the others are known.

		To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.

		*/

		M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;

		M = roundedDiv(M, 1000);



		/* M field has only 8 bits, reject value bigger than 8 bits */

		if (M < 256) {

			/* Calculate the actual clock for a given M & N */

			pllClk = pPLL->inputFreq * M / N / odPower / podPower;



			/* How much are we different from the requirement */

			diff = absDiff(pllClk, ulRequestClk);



			if (diff < bestDiff) {

				bestDiff = diff;



				/* Store M and N values */

				pPLL->M  = M;

				pPLL->N  = N;

				pPLL->OD = OD;



#ifdef VALIDATION_CHIP

			if (OD > 2)

				POD = 2;

			else

				POD = OD;

#endif



			pPLL->POD = POD;

			}

		}

	}

	}

	}



    /* Restore input frequency from Khz to hz unit */

	ulRequestClk *= 1000;

	pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */



    /* Return actual frequency that the PLL can set */

	ret = calcPLL(pPLL);

	return ret;

}











unsigned int formatPllReg(pll_value_t *pPLL)

{

	unsigned int ulPllReg = 0;

drivers/staging/sm750fb/ddk750_chip.h

+0 −1
Original line number Diff line number Diff line
@@ -73,7 +73,6 @@ initchip_param_t; 


logical_chip_type_t getChipType(void);

unsigned int calcPllValue(unsigned int request, pll_value_t *pll);

unsigned int calcPllValue2(unsigned int, pll_value_t *);

unsigned int formatPllReg(pll_value_t *pPLL);

void ddk750_set_mmio(void __iomem *, unsigned short, char);

unsigned int ddk750_getVMSize(void);