Loading drivers/gpu/msm/adreno-gpulist.h +2 −2 Original line number Diff line number Diff line Loading @@ -386,7 +386,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = 0, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU | ADRENO_IFPC | ADRENO_CONTENT_PROTECTION, ADRENO_CONTENT_PROTECTION, .sqefw_name = "a630_sqe.fw", .zap_name = "a640_zap", .gpudev = &adreno_a6xx_gpudev, Loading @@ -407,7 +407,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = ANY_ID, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU | ADRENO_IFPC | ADRENO_CONTENT_PROTECTION, ADRENO_CONTENT_PROTECTION, .sqefw_name = "a630_sqe.fw", .zap_name = "a640_zap", .gpudev = &adreno_a6xx_gpudev, Loading drivers/gpu/msm/adreno_a6xx.c +3 −3 Original line number Diff line number Diff line Loading @@ -1201,7 +1201,7 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, */ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) { if (!adreno_has_sptprac_gdsc(adreno_dev)) if (adreno_is_a608(adreno_dev)) return 0; return a6xx_gmu_sptprac_enable(adreno_dev); Loading @@ -1213,7 +1213,7 @@ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) */ static void a6xx_sptprac_disable(struct adreno_device *adreno_dev) { if (!adreno_has_sptprac_gdsc(adreno_dev)) if (adreno_is_a608(adreno_dev)) return; a6xx_gmu_sptprac_disable(adreno_dev); Loading Loading @@ -1384,7 +1384,7 @@ static int a6xx_soft_reset(struct adreno_device *adreno_dev) /* Clear GBIF client halt and CX arbiter halt */ adreno_deassert_gbif_halt(adreno_dev); a6xx_gmu_sptprac_enable(adreno_dev); a6xx_sptprac_enable(adreno_dev); return 0; } Loading drivers/gpu/msm/adreno_a6xx_gmu.c +5 −3 Original line number Diff line number Diff line Loading @@ -671,8 +671,9 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev) struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct gmu_device *gmu = KGSL_GMU_DEVICE(device); if (!gmu_core_gpmu_isenabled(device)) return -EINVAL; if (!gmu_core_gpmu_isenabled(device) || !adreno_has_sptprac_gdsc(adreno_dev)) return 0; gmu_core_regwrite(device, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, SPTPRAC_POWERON_CTRL_MASK); Loading @@ -698,7 +699,8 @@ void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev) struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct gmu_device *gmu = KGSL_GMU_DEVICE(device); if (!gmu_core_gpmu_isenabled(device)) if (!gmu_core_gpmu_isenabled(device) || !adreno_has_sptprac_gdsc(adreno_dev)) return; /* Ensure that retention is on */ Loading Loading
drivers/gpu/msm/adreno-gpulist.h +2 −2 Original line number Diff line number Diff line Loading @@ -386,7 +386,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = 0, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU | ADRENO_IFPC | ADRENO_CONTENT_PROTECTION, ADRENO_CONTENT_PROTECTION, .sqefw_name = "a630_sqe.fw", .zap_name = "a640_zap", .gpudev = &adreno_a6xx_gpudev, Loading @@ -407,7 +407,7 @@ static const struct adreno_gpu_core adreno_gpulist[] = { .minor = 0, .patchid = ANY_ID, .features = ADRENO_64BIT | ADRENO_RPMH | ADRENO_GPMU | ADRENO_IFPC | ADRENO_CONTENT_PROTECTION, ADRENO_CONTENT_PROTECTION, .sqefw_name = "a630_sqe.fw", .zap_name = "a640_zap", .gpudev = &adreno_a6xx_gpudev, Loading
drivers/gpu/msm/adreno_a6xx.c +3 −3 Original line number Diff line number Diff line Loading @@ -1201,7 +1201,7 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, */ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) { if (!adreno_has_sptprac_gdsc(adreno_dev)) if (adreno_is_a608(adreno_dev)) return 0; return a6xx_gmu_sptprac_enable(adreno_dev); Loading @@ -1213,7 +1213,7 @@ static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) */ static void a6xx_sptprac_disable(struct adreno_device *adreno_dev) { if (!adreno_has_sptprac_gdsc(adreno_dev)) if (adreno_is_a608(adreno_dev)) return; a6xx_gmu_sptprac_disable(adreno_dev); Loading Loading @@ -1384,7 +1384,7 @@ static int a6xx_soft_reset(struct adreno_device *adreno_dev) /* Clear GBIF client halt and CX arbiter halt */ adreno_deassert_gbif_halt(adreno_dev); a6xx_gmu_sptprac_enable(adreno_dev); a6xx_sptprac_enable(adreno_dev); return 0; } Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +5 −3 Original line number Diff line number Diff line Loading @@ -671,8 +671,9 @@ int a6xx_gmu_sptprac_enable(struct adreno_device *adreno_dev) struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct gmu_device *gmu = KGSL_GMU_DEVICE(device); if (!gmu_core_gpmu_isenabled(device)) return -EINVAL; if (!gmu_core_gpmu_isenabled(device) || !adreno_has_sptprac_gdsc(adreno_dev)) return 0; gmu_core_regwrite(device, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, SPTPRAC_POWERON_CTRL_MASK); Loading @@ -698,7 +699,8 @@ void a6xx_gmu_sptprac_disable(struct adreno_device *adreno_dev) struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct gmu_device *gmu = KGSL_GMU_DEVICE(device); if (!gmu_core_gpmu_isenabled(device)) if (!gmu_core_gpmu_isenabled(device) || !adreno_has_sptprac_gdsc(adreno_dev)) return; /* Ensure that retention is on */ Loading