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Commit 55546ac4 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: workaround SIC_IWR1 reset bug, by keeping MDMA0/1 always enabled in SIC_IWR1. 



This way we ensure that reboot succeeds.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent d3d0ac23

arch/blackfin/mach-common/ints-priority.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -1069,7 +1069,16 @@ int __init init_arch_irq(void) 




#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)

#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)

	bfin_write_SIC_IWR0(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR0(IWR_DISABLE_ALL);

#if defined(CONFIG_BF52x)

	/* BF52x system reset does not properly reset SIC_IWR1 which

	 * will screw up the bootrom as it relies on MDMA0/1 waking it

	 * up from IDLE instructions.  See this report for more info:

	 * http://blackfin.uclinux.org/gf/tracker/4323

	 */

	bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));

#else

	bfin_write_SIC_IWR1(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR1(IWR_DISABLE_ALL);

#endif

# ifdef CONFIG_BF54x

# ifdef CONFIG_BF54x

	bfin_write_SIC_IWR2(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR2(IWR_DISABLE_ALL);

# endif

# endif

arch/blackfin/mach-common/pm.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -84,7 +84,16 @@ void bfin_pm_suspend_standby_enter(void) 




#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)

#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561)

	bfin_write_SIC_IWR0(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR0(IWR_DISABLE_ALL);

#if defined(CONFIG_BF52x)

	/* BF52x system reset does not properly reset SIC_IWR1 which

	 * will screw up the bootrom as it relies on MDMA0/1 waking it

	 * up from IDLE instructions.  See this report for more info:

	 * http://blackfin.uclinux.org/gf/tracker/4323

	 */

	bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));

#else

	bfin_write_SIC_IWR1(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR1(IWR_DISABLE_ALL);

#endif

# ifdef CONFIG_BF54x

# ifdef CONFIG_BF54x

	bfin_write_SIC_IWR2(IWR_DISABLE_ALL);

	bfin_write_SIC_IWR2(IWR_DISABLE_ALL);

# endif

# endif