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Commit 54a849c6 authored by Deepak Katragadda's avatar Deepak Katragadda
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clk: qcom: CPU clock driver for SDM855



Add the OSM clock driver to control CPU clock scaling on SDM855.

Change-Id: I30265195c647a942799c9d09da7670d9d555a6c0
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 3295850b
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Qualcomm Technologies, Inc. OSM Bindings

Operating State Manager (OSM) is a hardware engine used by some Qualcomm
Technologies, Inc. (QTI) SoCs to manage frequency and voltage scaling
in hardware. OSM is capable of controlling frequency and voltage requests
for multiple clusters via the existence of multiple OSM domains.

Properties:
- compatible
	Usage:      required
	Value type: <string>
	Definition: must be "qcom,clk-cpu-osm".

- reg
	Usage:      required
	Value type: <prop-encoded-array>
	Definition: Addresses and sizes for the memory of the OSM controller.

- reg-names
	Usage:      required
	Value type: <stringlist>
	Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",
		    "osm_perfcl_base", and "osm_perfpcl_base".
		    Must be specified in the same order as the corresponding
		    addresses are specified in the reg property.

- l3-devs
	Usage: optional
	Value type: <phandle>
	Definition: List of phandles to devices that the OPP tables with the L3
		    frequency and voltage mappings are loaded for.

Example:
	clock_cpucc: qcom,cpucc {
		compatible = "qcom,clk-cpu-osm";
		reg = <0x18321000 0x1400>,
			<0x18323000 0x1400>,
			<0x18325800 0x1400>,
			<0x18327800 0x1400>;
		reg-names = "osm_l3_base", "osm_pwrcl_base",
			"osm_perfcl_base", "osm_perfpcl_base";

		l3-devs = <&phandle0 &phandle1 &phandle2>;

		#clock-cells = <1>;
	};
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@@ -240,3 +240,15 @@ config MSM_CAMCC_SDM855
	  SDM855 devices.
          Say Y if you want to support camera devices and functionality such as
	  capturing pictures.

config CLOCK_CPU_OSM
	tristate "OSM CPU Clock Controller"
	depends on COMMON_CLK_QCOM
	help
	 Support for the OSM clock controller.
	 Operating State Manager (OSM) is a hardware engine used by some
	 Qualcomm Technologies, Inc. (QTI) SoCs to manage frequency and
	 voltage scaling in hardware. OSM is capable of controlling
	 frequency and voltage requests for multiple clusters via the
	 existence of multiple OSM domains.
	 Say Y if you want to support OSM clocks.
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@@ -17,6 +17,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_CLOCK_CPU_OSM) += clk-cpu-osm.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
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@@ -16,16 +16,18 @@

#define L3_CLUSTER0_VOTE_CLK		0
#define L3_CLUSTER1_VOTE_CLK		1
#define L3_CLK							2
#define CPU0_PWRCL_CLK						3
#define CPU1_PWRCL_CLK						4
#define CPU2_PWRCL_CLK						5
#define CPU3_PWRCL_CLK						6
#define PWRCL_CLK						7
#define CPU4_PERFCL_CLK						8
#define CPU5_PERFCL_CLK						9
#define CPU6_PERFCL_CLK						10
#define CPU7_PERFCL_CLK						11
#define L3_MISC_VOTE_CLK		2
#define L3_CLK				3
#define CPU0_PWRCL_CLK			4
#define CPU1_PWRCL_CLK			5
#define CPU2_PWRCL_CLK			6
#define CPU3_PWRCL_CLK			7
#define PWRCL_CLK			8
#define CPU4_PERFCL_CLK			9
#define CPU5_PERFCL_CLK			10
#define CPU6_PERFCL_CLK			11
#define PERFCL_CLK			12
#define CPU7_PERFPCL_CLK		13
#define PERFPCL_CLK			14

#endif