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Commit 549eae58 authored by Prabhanjan Kandula's avatar Prabhanjan Kandula Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: fix exclusion rect control programming 



Current SDE driver does not reset respective exclusion rect
enable bit if a plane is un-staged. If a VIG plane is switched
from multi-rect mode with exclusion rect to non-multirect mode,
MDSS HW expects explicit clear of REC1 exclusion rect enable.
This change updates exclusion rect control programming as per
MDSS HW expectation.

Change-Id: Icf7e27cf3ca77541eadaeec97aed50d82fed3a80
Signed-off-by: default avatarPrabhanjan Kandula <pkandula@codeaurora.org>
parent 1ee5220d

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+6 −2
Original line number Diff line number Diff line
@@ -692,7 +692,8 @@ static void _sde_hw_sspp_setup_excl_rect(struct sde_hw_pipe *ctx, 
	u32 size, xy;

	u32 idx;

	u32 reg_xy, reg_size;

	u32 excl_ctrl, enable_bit;

	u32 excl_ctrl = BIT(0);

	u32 enable_bit;



	if (_sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx) || !excl_rect)

		return;
@@ -712,7 +713,10 @@ static void _sde_hw_sspp_setup_excl_rect(struct sde_hw_pipe *ctx, 
	xy = (excl_rect->y << 16) | (excl_rect->x);

	size = (excl_rect->h << 16) | (excl_rect->w);



	/* Set if multi-rect disabled, read+modify only if multi-rect enabled */

	if (rect_index != SDE_SSPP_RECT_SOLO)

		excl_ctrl = SDE_REG_READ(c, SSPP_EXCL_REC_CTL + idx);



	if (!size) {

		SDE_REG_WRITE(c, SSPP_EXCL_REC_CTL + idx,

				excl_ctrl & ~enable_bit);