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Commit 5436ad11 authored by Ashwini Muduganti's avatar Ashwini Muduganti
Browse files

Merge commit 'refs/changes/29/2485329/3' of ssh://git.quicinc.com:29418/kernel/msm-4.14 into HEAD 



Change-Id: I15eed530bf85a58deaa2bdcbcd4aedb4a7995631
Signed-off-by: default avatarAshwini Muduganti <amudug@codeaurora.org>
parents c79a93e1 7c9ebad0

Documentation/devicetree/bindings/net/macb.txt

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required properties: 
  Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on

  the Cadence GEM, or the generic form: "cdns,gem".

  Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.

  Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.

  Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.

  Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.

  Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 76

SUBLEVEL = 77

EXTRAVERSION =

NAME = Petit Gorille

arch/arm/boot/dts/sama5d3_emac.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
			};



			macb1: ethernet@f802c000 {

				compatible = "cdns,at91sam9260-macb", "cdns,macb";

				compatible = "atmel,sama5d3-macb", "cdns,at91sam9260-macb", "cdns,macb";

				reg = <0xf802c000 0x100>;

				interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;

				pinctrl-names = "default";

arch/arm/include/asm/assembler.h

+12 −0
Original line number Diff line number Diff line
@@ -447,11 +447,23 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) 
	.size \name , . - \name

	.endm



	.macro	csdb

#ifdef CONFIG_THUMB2_KERNEL

	.inst.w	0xf3af8014

#else

	.inst	0xe320f014

#endif

	.endm



	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req

#ifndef CONFIG_CPU_USE_DOMAINS

	adds	\tmp, \addr, #\size - 1

	sbcccs	\tmp, \tmp, \limit

	bcs	\bad

#ifdef CONFIG_CPU_SPECTRE

	movcs	\addr, #0

	csdb

#endif

#endif

	.endm

arch/arm/include/asm/barrier.h

+32 −0
Original line number Diff line number Diff line
@@ -17,6 +17,12 @@ 
#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")

#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")

#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")

#ifdef CONFIG_THUMB2_KERNEL

#define CSDB	".inst.w 0xf3af8014"

#else

#define CSDB	".inst	0xe320f014"

#endif

#define csdb() __asm__ __volatile__(CSDB : : : "memory")

#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6

#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \

				    : : "r" (0) : "memory")
@@ -37,6 +43,13 @@ 
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")

#endif



#ifndef CSDB

#define CSDB

#endif

#ifndef csdb

#define csdb()

#endif



#ifdef CONFIG_ARM_HEAVY_MB

extern void (*soc_mb)(void);

extern void arm_heavy_mb(void);
@@ -63,6 +76,25 @@ extern void arm_heavy_mb(void); 
#define __smp_rmb()	__smp_mb()

#define __smp_wmb()	dmb(ishst)



#ifdef CONFIG_CPU_SPECTRE

static inline unsigned long array_index_mask_nospec(unsigned long idx,

						    unsigned long sz)

{

	unsigned long mask;



	asm volatile(

		"cmp	%1, %2\n"

	"	sbc	%0, %1, %1\n"

	CSDB

	: "=r" (mask)

	: "r" (idx), "Ir" (sz)

	: "cc");



	return mask;

}

#define array_index_mask_nospec array_index_mask_nospec

#endif



#include <asm-generic/barrier.h>



#endif /* !__ASSEMBLY__ */