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Commit 542817fe authored by Namratha Siddappa's avatar Namratha Siddappa
Browse files

Merge remote-tracking branch 'quic/msm-4.14' into dev/msm-4.14-display_18apr 



* quic/msm-4.14:
  msm: npu: Update npu power level control
  defconfig: sm8150: enable spcom driver
  ARM: dts: msm: add spcom to sm8150
  dwc3-msm: Update maximum speed using extcon for high speed case only
  usb: dwc3-msm: Fix SuperSpeed when SuperSpeedPlus is supported
  drm/msm/sde: clear exclusion rect settings on lastclose
  drm/msm/sde: clear dim-layer settings when setting default value
  Revert "usb: dwc3: gadget: skip Set/Clear Halt when invalid"
  defconfig: sm8150: enable the smcinvoke driver
  drivers/soc/qcom: enable smcinvoke driver
  power: reset: Support Minidump select option in dump type
  soc: qcom: Register default dump entries to minidump table
  HID: uhid: remove custom locking from uhid_hid_open/close
  soc: qcom: add secure processor communication (spcom) driver
  adsprpc: validate VMID before hyp_assign during unmap
  clk: qcom: gcc: Add global clock controller driver for QCS405
  ARM: dts: msm: Add GCC, CPU & RPM device node for QCS405
  msm: ipa3: support HW stats query for LTE
  AndroidKernel: Add configuration for the LLVM path
  ARM: dts: msm: update PCIe clock frequencies for SM8150
  Revert "ARM: dts: msm: Add a test thermal zone for SM8150"
  ARM: dts: msm: Add MHI device tree nodes for sm8150
  msm: vidc: Remove inversion of video priority ctrl value
  defconfig: sm8150: Enable MHI host driver stack
  defconfig: sdmshrike: Enable various devfreq devices on sdmshrike
  defconfig: sdmshrike: Enable iommu debugfs interface on sdmshrike
  msm: kgsl: Write a cookie into HFI write buffer remainder
  ARM: dts: msm: add default display for sdmshrike
  ARM: dts: msm: add 7nm DSI pll dtsi entries for sdm shrike
  ARM: dts: msm: add displays supported by sdm shrike
  ARM: dts: msm: add display device tree file for sdmshrike
  ARM: dts: msm: add pinctrl information of display for SDMSHRIKE
  power: smb5: Make TYPEC_ATTACH_DETACH_IRQ wakeup capable
  power: smb5: update IRQ configuration
  clk: qcom: alpha-pll: Add support to adjust postdiv factor in slew ops
  defconfig: sdm: Update defconfig for sdm640
  rcu: Create RCU-specific workqueues with rescuers
  ARM: dts: msm: Enable coresight prng tpdm for sm8150
  tcp: clear tp->packets_out when purging write queue
  usb: gadget: f_qdss: Add support for mdm qdss channel
  drm/msm/sde: remove invalid excl_rect validations
  drm/msm/dsi-staging: avoid ctl soft reset when cont-splash is enabled
  drm/msm/sde: avoid disabling clks/bw when cont-splash is enabled
  ARM: dts: msm: Add SLPI PIL node for sdmshrike target
  ARM: dts: msm: Add NPU device configuration on SM8150
  msm: npu: Add driver functionality to support NPU
  defconfig: sdmshrike: enable compilation of SDE display driver
  defconfig: sm8150: Enable CMA debugfs
  soc: qcom: pil: Allow timeouts for graceful subsystem shutdown
  soc: qcom: pil: Expose function to get subsys_device pointer
  ARM: dts: msm: update the DisplayPort AUX settings for sm8150
  drm/msm/dp: update the DP PHY and controller programming for sm8150
  ARM: dts: msm: Fix UBWC configuration for camera on sm8150
  ARM: dts: msm: Enable video governor for bw calculation on sm8150
  ARM: dts: msm: Update video clock config for sm8150
  soc: qcom: Use ToC design for Minidump support
  elf: Add elf headers helpers support
  soc: qcom: Add Minidump support
  ARM: dts: msm: Enable SMMU S1 functionality with USB on SM8150
  qbt1000: Fix for incorrect buffer size check and integer overflow
  qbt1000: Terminate fingerprint TA name with null
  ARM: dts: msm: Add bluetooth device node for sm8150
  power: qcom: Add support for FG software algorithms
  power_supply: add cycle_counts property
  dwc3: gadget: remove usage of wait_event_lock_irq()
  clk: qcom: gdsc: Fix issue with dereferencing NULL pointer in gdsc APIs
  drivers: thermal: Aggregate userspace mitigation request
  ARM: dts: msm: Add GPU thermal config for SM8150
  ARM: dts: msm: Add vbat and soc mitigation for SM8150
  msm: ipa: enable hdr_metadata_reg_valid for usb
  iommu/iova: Limit IOVA alignment using CONFIG_ARM64_DMA_IOMMU_ALIGNMENT
  ARM: dts: msm: update current limit for wcd9360 in SM8150
  skb: printing port numbers with gso trace events
  skb: Adding trace event for gso.
  net: Reset NAPI bit if IPI failed
  tun: Set CHECKSUM_UNNECESSARY if userspace passes this indication
  net: add a per-cpu counter for the number of frames coalesced in GRO
  net: Fail explicit bind to local reserved ports
  net: Indicate whether a socket is a transparent socket
  net: udp: Adjust UDP socket state for encapsulation sockets
  mmc: host: Kconfig: Enable cmdq config
  adsprpc: optimize number of SGL entries during map create
  drivers: arm: cpuidle: support ARMv7 targets for lpm governor

Change-Id: I70eda772be33d485dfd8629e6823ee1557f90e0d
Signed-off-by: default avatarNamratha Siddappa <namratha@codeaurora.org>
parents c5c15b8b 387e9dc0

AndroidKernel.mk

+14 −0
Original line number Diff line number Diff line
@@ -47,6 +47,20 @@ else 
KERNEL_CROSS_COMPILE := $(TARGET_KERNEL_CROSS_COMPILE_PREFIX)

endif



ifeq ($(KERNEL_LLVM_SUPPORT), true)

  ifeq ($(KERNEL_SD_LLVM_SUPPORT), true)  #Using sd-llvm compiler

    ifeq ($(shell echo $(SDCLANG_PATH_2) | head -c 1),/)

       KERNEL_LLVM_BIN := $(SDCLANG_PATH_2)/clang

    else

       KERNEL_LLVM_BIN := $(ANDROID_BUILD_TOP)/$(SDCLANG_PATH_2)/clang

    endif

    $(warning "Using sdllvm" $(KERNEL_LLVM_BIN))

  else

     KERNEL_LLVM_BIN := $(ANDROID_BUILD_TOP)/$(CLANG) #Using aosp-llvm compiler

    $(warning "Using aosp-llvm" $(KERNEL_LLVM_BIN))

  endif

endif



ifeq ($(TARGET_PREBUILT_KERNEL),)



KERNEL_GCC_NOANDROID_CHK := $(shell (echo "int main() {return 0;}" | $(KERNEL_CROSS_COMPILE)gcc -E -mno-android - > /dev/null 2>&1 ; echo $$?))

Documentation/devicetree/bindings/arm/msm/spcom.txt

0 → 100644
+11 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. Secure Proccessor Communication (spcom)



Required properties:

-compatible : should be "qcom,spcom"

-qcom,spcom-ch-names: predefined channels name string



Example:

    qcom,spcom {

            compatible = "qcom,spcom";

            qcom,spcom-ch-names = "sp_kernel" , "sp_ssr";

    };

Documentation/devicetree/bindings/clock/qcom,gcc.txt

+2 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ Required properties : 
			"qcom,gcc-mdm9615"

			"qcom,gcc-sm8150"

			"qcom,gcc-sdmshrike"

			"qcom,gcc-qcs405"

			"qcom,gcc-mdss-qcs405"



- reg : shall contain base register location and length

- #clock-cells : shall contain 1

Documentation/devicetree/bindings/media/msm-npu-pwrlevels.txt

0 → 100644
+164 −0
Original line number Diff line number Diff line 
Qualcomm Technologies, Inc. NPU powerlevels



Powerlevels are defined in sets by qcom,npu-pwrlevels. Each powerlevel defines

a series of clock frequencies. These frequencies are for the corresponding

clocks in the clocks property of the msm_npu device.



qcom,npu-pwrlevels bindings:



Required Properties:

- #address-cells: Should be set to 1

- #size-cells: Should be set to 0

- compatible: Must be qcom,npu-pwrlevels

- initial-pwrlevel: NPU initial wakeup power level, this is the index of the

	child node.



qcom,npu-pwrlevel: This is a child node defining power levels.

qcom,npu-pwrlevels must contain at least one power level node. Each child node

has the following properties:



Required Properties:

- reg: Index of the powerlevel (0 = lowest performance)

- clk-freq: List of clock frequencies (in Hz) of each clock for the current

	powerlevel. List of clocks and order described in:

	Documentation/devicetree/bindings/media/msm-npu.txt



Example:

	qcom,npu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "qcom,npu-pwrlevels";

		initial-pwrlevel = <4>;

		qcom,npu-pwrlevel@0 {

			reg = <0>;

			clk-freq = <9600000

					9600000

					19200000

					19200000

					19200000

					19200000

					9600000

					60000000

					19200000

					19200000

					30000000

					19200000

					19200000

					19200000

					19200000

					19200000

					9600000

					19200000

					0>;

		};

		qcom,npu-pwrlevel@1 {

			reg = <1>;

			clk-freq = <300000000

					300000000

					19200000

					100000000

					19200000

					19200000

					300000000

					150000000

					19200000

					19200000

					60000000

					100000000

					100000000

					37500000

					100000000

					19200000

					300000000

					19200000

					0>;

		};

		qcom,npu-pwrlevel@2 {

			reg = <2>;

			clk-freq = <350000000

					350000000

					19200000

					150000000

					19200000

					19200000

					350000000

					200000000

					37500000

					19200000

					120000000

					150000000

					150000000

					75000000

					150000000

					19200000

					350000000

					19200000

					0>;

		};

		qcom,npu-pwrlevel@3 {

			reg = <3>;

			clk-freq = <400000000

					400000000

					19200000

					200000000

					19200000

					19200000

					400000000

					300000000

					37500000

					19200000

					120000000

					200000000

					200000000

					75000000

					200000000

					19200000

					400000000

					19200000

					0>;

		};

		qcom,npu-pwrlevel@4 {

			reg = <4>;

			clk-freq = <600000000

					600000000

					19200000

					300000000

					19200000

					19200000

					600000000

					403000000

					75000000

					19200000

					240000000

					300000000

					300000000

					150000000

					300000000

					19200000

					600000000

					19200000

					0>;

		};

		qcom,npu-pwrlevel@5 {

			reg = <5>;

			clk-freq = <715000000

					715000000

					19200000

					350000000

					19200000

					19200000

					715000000

					533000000

					75000000

					19200000

					240000000

					350000000

					350000000

					150000000

					350000000

					19200000

					715000000

					19200000

					0>;

		};

	};

Documentation/devicetree/bindings/media/msm-npu.txt

+208 −23
Original line number Diff line number Diff line
@@ -3,14 +3,18 @@ 
NPU (Neural Network Processing Unit) applies neural network processing



Required properties:

- compatible:

    - "qcom,msm-npu"

- compatible: Must be "qcom,msm-npu"

- reg: Specify offset and length of the device register sets.

- reg-names: Names corresponding to the defined register sets.

	- "npu_base": npu base registers

- interrupts: Specify the npu interrupts.

- interrupt-names: should specify relevant names to each interrupts

	property defined.

- cache-slice-names: A set of names that identify the usecase names of a

	client that uses cache slice. These strings are used to look up the

	cache slice entries by name

- cache-slices: The tuple has phandle to llcc device as the first argument

	and the second argument is the usecase id of the client

- clocks: clocks required for the device.

- clock-names: names of clocks required for the device.

- vdd-supply: Phandle for vdd regulator device node
@@ -20,24 +24,205 @@ Required properties: 
	during proxy voting/unvoting.

- qcom,vdd_'reg'-uV-uA: Voltage and current values for the 'reg' regulator,

	e.g. qcom,vdd_cx-uV-uA.



- mboxes: Phandle array for mailbox controllers to be used for IPC

- mbox-names: names of each mailboxes

- #cooling-cells: Should be set to 2

- qcom,npubw-dev: a phandle to a device representing bus bandwidth requirements

	(see devbw.txt)

- qcom,npu-pwrlevels: Container for NPU power levels

	(see msm-npu-pwrlevels.txt)

Example:

	msm_npu: qcom,msm_npu {

	msm_npu: qcom,msm_npu@9800000 {

		compatible = "qcom,msm-npu";

		status = "ok";

		reg = <0x9800000 0x800000>;

		reg-names = "npu_base";

		interrupts = <0 346 0>;

		interrupt-names = "single";

		clocks = <&clock_npucc NPU_CC_XO_CLK>,

					<&clock_npucc NPU_CC_NPU_CORE_CLK>,

					<&clock_npucc NPU_CC_CAL_DP_CLK>,

		interrupts = <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>;

		iommus = <&apps_smmu 0x1461 0x0>, <&apps_smmu 0x2061 0x0>;

		cache-slice-names = "npu";

		cache-slices = <&llcc 23>;

		clocks = <&clock_npucc NPU_CC_CAL_DP_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CLK_SRC>,

				<&clock_npucc NPU_CC_XO_CLK>,

				<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,

				<&clock_npucc NPU_CC_BTO_CORE_CLK>,

				<&clock_npucc NPU_CC_BWMON_CLK>,

				<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,

				<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,

					<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>;

		clock-names = "xo", "core", "cal_dp", "armwic",

						"axi", "ahb";

				<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK>,

				<&clock_npucc NPU_CC_NPU_CORE_CLK_SRC>,

				<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_CLK>,

				<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,

				<&clock_npucc NPU_CC_PERF_CNT_CLK>,

				<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,

				<&clock_npucc NPU_CC_SLEEP_CLK>;

		clock-names = "cal_dp_clk",

				"cal_dp_clk_src",

				"xo_clk",

				"armwic_core_clk",

				"bto_core_clk",

				"bwmon_clk",

				"cal_dp_cdc_clk",

				"comp_noc_axi_clk",

				"conf_noc_ahb_clk",

				"npu_core_apb_clk",

				"npu_core_atb_clk",

				"npu_core_clk",

				"npu_core_clk_src",

				"npu_core_cti_clk",

				"npu_cpc_clk",

				"npu_cpc_timer_clk",

				"perf_cnt_clk",

				"qtimer_core_clk",

				"sleep_clk";

		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&pm855l_s6_level>;

		qcom,proxy-reg-names ="vdd", "vdd_cx";

		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;

		mbox-names = "npu_low", "npu_high";

		#cooling-cells = <2>;

		qcom,npubw-dev = <&npu_npu_ddr_bw>;

		qcom,npu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,npu-pwrlevels";

			initial-pwrlevel = <4>;

			qcom,npu-pwrlevel@0 {

				reg = <0>;

				clk-freq = <9600000

						9600000

						19200000

						19200000

						19200000

						19200000

						9600000

						60000000

						19200000

						19200000

						30000000

						19200000

						19200000

						19200000

						19200000

						19200000

						9600000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@1 {

				reg = <1>;

				clk-freq = <300000000

						300000000

						19200000

						100000000

						19200000

						19200000

						300000000

						150000000

						19200000

						19200000

						60000000

						100000000

						100000000

						37500000

						100000000

						19200000

						300000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@2 {

				reg = <2>;

				clk-freq = <350000000

						350000000

						19200000

						150000000

						19200000

						19200000

						350000000

						200000000

						37500000

						19200000

						120000000

						150000000

						150000000

						75000000

						150000000

						19200000

						350000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@3 {

				reg = <3>;

				clk-freq = <400000000

						400000000

						19200000

						200000000

						19200000

						19200000

						400000000

						300000000

						37500000

						19200000

						120000000

						200000000

						200000000

						75000000

						200000000

						19200000

						400000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@4 {

				reg = <4>;

				clk-freq = <600000000

						600000000

						19200000

						300000000

						19200000

						19200000

						600000000

						403000000

						75000000

						19200000

						240000000

						300000000

						300000000

						150000000

						300000000

						19200000

						600000000

						19200000

						0>;

			};

			qcom,npu-pwrlevel@5 {

				reg = <5>;

				clk-freq = <715000000

						715000000

						19200000

						350000000

						19200000

						19200000

						715000000

						533000000

						75000000

						19200000

						240000000

						350000000

						350000000

						150000000

						350000000

						19200000

						715000000

						19200000

						0>;

			};

		};

	};