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Commit 53f67697 authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
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MIPS: MSI: Update MSI handling for XLP 



The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.

PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8887/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent a3613be4

arch/mips/pci/msi-xlp.c

+10 −9
Original line number Diff line number Diff line
@@ -178,13 +178,6 @@ static void xlp_msi_mask_ack(struct irq_data *d) 
	else

		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);



	/* Ack at eirr and PIC */

	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));

	if (cpu_is_xlp9xx())

		nlm_pic_ack(md->node->picbase,

				PIC_9XX_IRT_PCIE_LINK_INDEX(link));

	else

		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));

}



static struct irq_chip xlp_msi_chip = {
@@ -230,8 +223,6 @@ static void xlp_msix_mask_ack(struct irq_data *d) 
	}

	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);



	/* Ack at eirr and PIC */

	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));

	if (!cpu_is_xlp9xx())

		nlm_pic_ack(md->node->picbase,

				PIC_IRT_PCIE_MSIX_INDEX(msixvec));
@@ -541,6 +532,14 @@ void nlm_dispatch_msi(int node, int lirq) 
		do_IRQ(irqbase + i);

		status &= status - 1;

	}



	/* Ack at eirr and PIC */

	ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));

	if (cpu_is_xlp9xx())

		nlm_pic_ack(md->node->picbase,

				PIC_9XX_IRT_PCIE_LINK_INDEX(link));

	else

		nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));

}



void nlm_dispatch_msix(int node, int lirq)
@@ -567,4 +566,6 @@ void nlm_dispatch_msix(int node, int lirq) 
		do_IRQ(irqbase + i);

		status &= status - 1;

	}

	/* Ack at eirr and PIC */

	ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));

}