Loading drivers/gpu/drm/msm/msm_smmu.c +4 −5 Original line number Diff line number Diff line Loading @@ -173,13 +173,12 @@ static int msm_smmu_map(struct msm_mmu *mmu, uint64_t iova, { struct msm_smmu *smmu = to_msm_smmu(mmu); struct msm_smmu_client *client = msm_smmu_to_client(smmu); size_t ret; size_t ret = 0; if (sgt && sgt->sgl) { ret = iommu_map_sg(client->mmu_mapping->domain, iova, sgt->sgl, sgt->nents, prot); WARN_ON(ret < 0); if (sgt && sgt->sgl) { DRM_DEBUG("%pad/0x%x/0x%x/\n", &sgt->sgl->dma_address, sgt->sgl->dma_length, prot); SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length, Loading drivers/gpu/drm/msm/sde/sde_encoder.c +5 −3 Original line number Diff line number Diff line Loading @@ -1195,7 +1195,7 @@ static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc) const struct sde_rect *roi = &sde_enc->cur_conn_roi; struct msm_mode_info mode_info; struct msm_display_dsc_info *dsc = NULL; struct sde_hw_ctl *hw_ctl = enc_master->hw_ctl; struct sde_hw_ctl *hw_ctl; struct sde_ctl_dsc_cfg cfg; int rc; Loading @@ -1210,6 +1210,8 @@ static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc) return -EINVAL; } hw_ctl = enc_master->hw_ctl; memset(&cfg, 0, sizeof(cfg)); dsc = &mode_info.comp_info.dsc_info; _sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h); Loading Loading @@ -1582,6 +1584,8 @@ void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, struct sde_encoder_virt *sde_enc; int i, rc = 0; sde_enc = to_sde_encoder_virt(phys_enc->parent); if (!sde_enc) { SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL); return; Loading @@ -1592,8 +1596,6 @@ void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, return; } sde_enc = to_sde_encoder_virt(phys_enc->parent); drm_enc = &sde_enc->base; /* this pointers are checked in virt_enable_helper */ priv = drm_enc->dev->dev_private; Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static void _sde_encoder_phys_cmd_update_flush_mask( struct sde_hw_ctl *ctl; bool merge_3d_enable = false; if (!phys_enc && !phys_enc->hw_intf && !phys_enc->hw_pp) if (!phys_enc || !phys_enc->hw_intf || !phys_enc->hw_pp) return; cmd_enc = to_sde_encoder_phys_cmd(phys_enc); Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +1 −0 Original line number Diff line number Diff line Loading @@ -841,6 +841,7 @@ static void sde_encoder_phys_vid_get_hw_resources( return; } vid_enc = to_sde_encoder_phys_vid(phys_enc); SDE_DEBUG_VIDENC(vid_enc, "\n"); hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; } Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +1 −1 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ static int _sde_encoder_phys_wb_init_internal_fb( /* allocate gem tracking object */ nplanes = drm_format_num_planes(pixel_format); if (nplanes > SDE_MAX_PLANES) { if (nplanes >= SDE_MAX_PLANES) { SDE_ERROR("requested format has too many planes\n"); return -EINVAL; } Loading Loading
drivers/gpu/drm/msm/msm_smmu.c +4 −5 Original line number Diff line number Diff line Loading @@ -173,13 +173,12 @@ static int msm_smmu_map(struct msm_mmu *mmu, uint64_t iova, { struct msm_smmu *smmu = to_msm_smmu(mmu); struct msm_smmu_client *client = msm_smmu_to_client(smmu); size_t ret; size_t ret = 0; if (sgt && sgt->sgl) { ret = iommu_map_sg(client->mmu_mapping->domain, iova, sgt->sgl, sgt->nents, prot); WARN_ON(ret < 0); if (sgt && sgt->sgl) { DRM_DEBUG("%pad/0x%x/0x%x/\n", &sgt->sgl->dma_address, sgt->sgl->dma_length, prot); SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length, Loading
drivers/gpu/drm/msm/sde/sde_encoder.c +5 −3 Original line number Diff line number Diff line Loading @@ -1195,7 +1195,7 @@ static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc) const struct sde_rect *roi = &sde_enc->cur_conn_roi; struct msm_mode_info mode_info; struct msm_display_dsc_info *dsc = NULL; struct sde_hw_ctl *hw_ctl = enc_master->hw_ctl; struct sde_hw_ctl *hw_ctl; struct sde_ctl_dsc_cfg cfg; int rc; Loading @@ -1210,6 +1210,8 @@ static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc) return -EINVAL; } hw_ctl = enc_master->hw_ctl; memset(&cfg, 0, sizeof(cfg)); dsc = &mode_info.comp_info.dsc_info; _sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h); Loading Loading @@ -1582,6 +1584,8 @@ void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, struct sde_encoder_virt *sde_enc; int i, rc = 0; sde_enc = to_sde_encoder_virt(phys_enc->parent); if (!sde_enc) { SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL); return; Loading @@ -1592,8 +1596,6 @@ void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc, return; } sde_enc = to_sde_encoder_virt(phys_enc->parent); drm_enc = &sde_enc->base; /* this pointers are checked in virt_enable_helper */ priv = drm_enc->dev->dev_private; Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_cmd.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static void _sde_encoder_phys_cmd_update_flush_mask( struct sde_hw_ctl *ctl; bool merge_3d_enable = false; if (!phys_enc && !phys_enc->hw_intf && !phys_enc->hw_pp) if (!phys_enc || !phys_enc->hw_intf || !phys_enc->hw_pp) return; cmd_enc = to_sde_encoder_phys_cmd(phys_enc); Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +1 −0 Original line number Diff line number Diff line Loading @@ -841,6 +841,7 @@ static void sde_encoder_phys_vid_get_hw_resources( return; } vid_enc = to_sde_encoder_phys_vid(phys_enc); SDE_DEBUG_VIDENC(vid_enc, "\n"); hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; } Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +1 −1 Original line number Diff line number Diff line Loading @@ -1178,7 +1178,7 @@ static int _sde_encoder_phys_wb_init_internal_fb( /* allocate gem tracking object */ nplanes = drm_format_num_planes(pixel_format); if (nplanes > SDE_MAX_PLANES) { if (nplanes >= SDE_MAX_PLANES) { SDE_ERROR("requested format has too many planes\n"); return -EINVAL; } Loading