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Commit 536fc234 authored by Changbin Du's avatar Changbin Du Committed by Zhenyu Wang
Browse files

drm/i915/gvt: move cfg space inititation function to cfg_space.c 



Move the configuration space inititation function setup_vgpu_cfg_space()
in vgpu.c to dedicated source file cfg_space.c, and rename the function
as intel_vgpu_init_cfg_space().

Signed-off-by: default avatarChangbin Du <changbin.du@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent b611581b

drivers/gpu/drm/i915/gvt/cfg_space.c

+49 −0
Original line number Diff line number Diff line
@@ -282,3 +282,52 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
	}

	return 0;

}



/**

 * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU

 *

 * @vgpu: a vGPU

 * @primary: is the vGPU presented as primary

 *

 */

void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,

			       bool primary)

{

	struct intel_gvt *gvt = vgpu->gvt;

	const struct intel_gvt_device_info *info = &gvt->device_info;

	u16 *gmch_ctl;

	int i;



	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,

	       info->cfg_space_size);



	if (!primary) {

		vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =

			INTEL_GVT_PCI_CLASS_VGA_OTHER;

		vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =

			INTEL_GVT_PCI_CLASS_VGA_OTHER;

	}



	/* Show guest that there isn't any stolen memory.*/

	gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);

	*gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);



	intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,

				 gvt_aperture_pa_base(gvt), true);



	vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO

					     | PCI_COMMAND_MEMORY

					     | PCI_COMMAND_MASTER);

	/*

	 * Clear the bar upper 32bit and let guest to assign the new value

	 */

	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);

	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);

	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);



	for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) {

		vgpu->cfg_space.bar[i].size = pci_resource_len(

					      gvt->dev_priv->drm.pdev, i * 2);

		vgpu->cfg_space.bar[i].tracked = false;

	}

}

drivers/gpu/drm/i915/gvt/gvt.h

+2 −0
Original line number Diff line number Diff line
@@ -412,6 +412,8 @@ int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 
int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,

			     unsigned long *g_index);



void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,

		bool primary);

int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,

		void *p_data, unsigned int bytes);

drivers/gpu/drm/i915/gvt/vgpu.c

+1 −43
Original line number Diff line number Diff line
@@ -66,48 +66,6 @@ int setup_vgpu_mmio(struct intel_vgpu *vgpu) 
	return 0;

}



static void setup_vgpu_cfg_space(struct intel_vgpu *vgpu,

	struct intel_vgpu_creation_params *param)

{

	struct intel_gvt *gvt = vgpu->gvt;

	const struct intel_gvt_device_info *info = &gvt->device_info;

	u16 *gmch_ctl;

	int i;



	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,

	       info->cfg_space_size);



	if (!param->primary) {

		vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =

			INTEL_GVT_PCI_CLASS_VGA_OTHER;

		vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =

			INTEL_GVT_PCI_CLASS_VGA_OTHER;

	}



	/* Show guest that there isn't any stolen memory.*/

	gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);

	*gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);



	intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,

				 gvt_aperture_pa_base(gvt), true);



	vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO

					     | PCI_COMMAND_MEMORY

					     | PCI_COMMAND_MASTER);

	/*

	 * Clear the bar upper 32bit and let guest to assign the new value

	 */

	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);

	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);

	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);



	for (i = 0; i < INTEL_GVT_MAX_BAR_NUM; i++) {

		vgpu->cfg_space.bar[i].size = pci_resource_len(

					      gvt->dev_priv->drm.pdev, i * 2);

		vgpu->cfg_space.bar[i].tracked = false;

	}

}



void populate_pvinfo_page(struct intel_vgpu *vgpu)

{

	/* setup the ballooning information */
@@ -300,7 +258,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt, 
	vgpu->gvt = gvt;

	bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);



	setup_vgpu_cfg_space(vgpu, param);

	intel_vgpu_init_cfg_space(vgpu, param->primary);



	ret = setup_vgpu_mmio(vgpu);

	if (ret)