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Commit 52f8c938 authored by Kalle Valo's avatar Kalle Valo
Browse files

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git 

ath.git patches for 4.13. Major changes:

wil6210

* add low level RF sector interface via nl80211 vendor commands

* add module parameter ftm_mode to load separate firmware for factory
  testing

* support devices with different PCIe bar size

* add support for PCIe D3hot in system suspend

* remove ioctl interface which should not be in a wireless driver

ath10k

* go back to using dma_alloc_coherent() for firmware scratch memory

* add per chain RSSI reporting
parents 3f426c96 a520b49e

drivers/net/wireless/ath/ath10k/bmi.h

+4 −2
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ enum bmi_cmd_id { 
#define BMI_NVRAM_SEG_NAME_SZ 16



#define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10

#define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000

#define BMI_PARAM_FLASH_SECTION_ALL 0x10000



#define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK   0x7c00

#define ATH10K_BMI_BOARD_ID_FROM_OTP_LSB    10
@@ -188,8 +190,8 @@ struct bmi_target_info { 
	u32 type;

};



/* in msec */

#define BMI_COMMUNICATION_TIMEOUT_HZ (2 * HZ)

/* in jiffies */

#define BMI_COMMUNICATION_TIMEOUT_HZ (3 * HZ)



#define BMI_CE_NUM_TO_TARG 0

#define BMI_CE_NUM_TO_HOST 1

drivers/net/wireless/ath/ath10k/ce.c

+105 −63
Original line number Diff line number Diff line
@@ -59,205 +59,243 @@ 
 * the buffer is sent/received.

 */



static inline unsigned int

ath10k_set_ring_byte(unsigned int offset,

		     struct ath10k_hw_ce_regs_addr_map *addr_map)

{

	return ((offset << addr_map->lsb) & addr_map->mask);

}



static inline unsigned int

ath10k_get_ring_byte(unsigned int offset,

		     struct ath10k_hw_ce_regs_addr_map *addr_map)

{

	return ((offset & addr_map->mask) >> (addr_map->lsb));

}



static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,

						       u32 ce_ctrl_addr,

						       unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->dst_wr_index_addr, n);

}



static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,

						      u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS);

	return ath10k_pci_read32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->dst_wr_index_addr);

}



static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,

						      u32 ce_ctrl_addr,

						      unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->sr_wr_index_addr, n);

}



static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS);

	return ath10k_pci_read32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->sr_wr_index_addr);

}



static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_SRRI_ADDRESS);

	return ath10k_pci_read32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->current_srri_addr);

}



static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,

						    u32 ce_ctrl_addr,

						    unsigned int addr)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->sr_base_addr, addr);

}



static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->sr_size_addr, n);

}



static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,

					       u32 ce_ctrl_addr,

					       unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32((ar),

					   (ce_ctrl_addr) + CE_CTRL1_ADDRESS);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;

	u32 ctrl1_addr = ath10k_pci_read32(ar,

					   ce_ctrl_addr + ctrl_regs->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr &  ~CE_CTRL1_DMAX_LENGTH_MASK) |

			   CE_CTRL1_DMAX_LENGTH_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr &  ~(ctrl_regs->dmax->mask)) |

			   ath10k_set_ring_byte(n, ctrl_regs->dmax));

}



static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,

						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |

			   ath10k_set_ring_byte(n, ctrl_regs->src_ring));

}



static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,

						     u32 ce_ctrl_addr,

						     unsigned int n)

{

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS);

	struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;

	u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,

			   (ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |

			   CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr,

			   (ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |

			   ath10k_set_ring_byte(n, ctrl_regs->dst_ring));

}



static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,

						     u32 ce_ctrl_addr)

{

	return ath10k_pci_read32(ar, ce_ctrl_addr + CURRENT_DRRI_ADDRESS);

	return ath10k_pci_read32(ar, ce_ctrl_addr +

				 ar->hw_ce_regs->current_drri_addr);

}



static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,

						     u32 ce_ctrl_addr,

						     u32 addr)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->dr_base_addr, addr);

}



static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,

						u32 ce_ctrl_addr,

						unsigned int n)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);

	ath10k_pci_write32(ar, ce_ctrl_addr +

			ar->hw_ce_regs->dr_size_addr, n);

}



static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,

						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_HIGH_MASK) |

			   SRC_WATERMARK_HIGH_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_high->mask)) |

			   (ath10k_set_ring_byte(n, srcr_wm->wm_high)));

}



static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,

						  u32 ce_ctrl_addr,

						  unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,

			   (addr & ~SRC_WATERMARK_LOW_MASK) |

			   SRC_WATERMARK_LOW_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr,

			   (addr & ~(srcr_wm->wm_low->mask)) |

			   (ath10k_set_ring_byte(n, srcr_wm->wm_low)));

}



static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,

						    u32 ce_ctrl_addr,

						    unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_HIGH_MASK) |

			   DST_WATERMARK_HIGH_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_high->mask)) |

			   (ath10k_set_ring_byte(n, dstr_wm->wm_high)));

}



static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,

						   u32 ce_ctrl_addr,

						   unsigned int n)

{

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS);

	struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;

	u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,

			   (addr & ~DST_WATERMARK_LOW_MASK) |

			   DST_WATERMARK_LOW_SET(n));

	ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr,

			   (addr & ~(dstr_wm->wm_low->mask)) |

			   (ath10k_set_ring_byte(n, dstr_wm->wm_low)));

}



static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;

	u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +

					ar->hw_ce_regs->host_ie_addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);

	ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			   host_ie_addr | host_ie->copy_complete->mask);

}



static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,

							u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

	struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;

	u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +

					ar->hw_ce_regs->host_ie_addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);

	ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			   host_ie_addr & ~(host_ie->copy_complete->mask));

}



static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,

						    u32 ce_ctrl_addr)

{

	u32 host_ie_addr = ath10k_pci_read32(ar,

					     ce_ctrl_addr + HOST_IE_ADDRESS);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;

	u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +

					ar->hw_ce_regs->host_ie_addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,

			   host_ie_addr & ~CE_WATERMARK_MASK);

	ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,

			   host_ie_addr & ~(wm_regs->wm_mask));

}



static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,

					       u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ath10k_pci_read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;

	u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +

					ar->hw_ce_regs->misc_ie_addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr | CE_ERROR_MASK);

	ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			   misc_ie_addr | misc_regs->err_mask);

}



static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,

						u32 ce_ctrl_addr)

{

	u32 misc_ie_addr = ath10k_pci_read32(ar,

					     ce_ctrl_addr + MISC_IE_ADDRESS);

	struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;

	u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +

					ar->hw_ce_regs->misc_ie_addr);



	ath10k_pci_write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,

			   misc_ie_addr & ~CE_ERROR_MASK);

	ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,

			   misc_ie_addr & ~(misc_regs->err_mask));

}



static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,

						     u32 ce_ctrl_addr,

						     unsigned int mask)

{

	ath10k_pci_write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;



	ath10k_pci_write32(ar, ce_ctrl_addr + wm_regs->addr, mask);

}



/*
@@ -594,6 +632,7 @@ int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 
	unsigned int nentries_mask = src_ring->nentries_mask;

	unsigned int sw_index = src_ring->sw_index;

	unsigned int read_index;

	struct ce_desc *desc;



	if (src_ring->hw_index == sw_index) {

		/*
@@ -623,6 +662,9 @@ int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state, 


	/* sanity */

	src_ring->per_transfer_context[sw_index] = NULL;

	desc = CE_SRC_RING_TO_DESC(src_ring->base_addr_owner_space,

				   sw_index);

	desc->nbytes = 0;



	/* Update sw_index */

	sw_index = CE_RING_IDX_INCR(nentries_mask, sw_index);
@@ -715,13 +757,13 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
{

	struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);

	struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];

	struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;

	u32 ctrl_addr = ce_state->ctrl_addr;



	spin_lock_bh(&ar_pci->ce_lock);



	/* Clear the copy-complete interrupts that will be handled here. */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,

					  HOST_IS_COPY_COMPLETE_MASK);

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->cc_mask);



	spin_unlock_bh(&ar_pci->ce_lock);
@@ -737,7 +779,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) 
	 * Misc CE interrupts are not being handled, but still need

	 * to be cleared.

	 */

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);

	ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);



	spin_unlock_bh(&ar_pci->ce_lock);

}

drivers/net/wireless/ath/ath10k/ce.h

+0 −132
Original line number Diff line number Diff line
@@ -263,143 +263,11 @@ struct ce_attr { 
	void (*recv_cb)(struct ath10k_ce_pipe *);

};



#define SR_BA_ADDRESS		0x0000

#define SR_SIZE_ADDRESS		0x0004

#define DR_BA_ADDRESS		0x0008

#define DR_SIZE_ADDRESS		0x000c

#define CE_CMD_ADDRESS		0x0018



#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB	17

#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB	17

#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK	0x00020000

#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \

	(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \

	CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)



#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB	16

#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB	16

#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK	0x00010000

#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \

	(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \

	 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)

#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \

	(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \

	 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)



#define CE_CTRL1_DMAX_LENGTH_MSB		15

#define CE_CTRL1_DMAX_LENGTH_LSB		0

#define CE_CTRL1_DMAX_LENGTH_MASK		0x0000ffff

#define CE_CTRL1_DMAX_LENGTH_GET(x) \

	(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)

#define CE_CTRL1_DMAX_LENGTH_SET(x) \

	(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)



#define CE_CTRL1_ADDRESS			0x0010

#define CE_CTRL1_HW_MASK			0x0007ffff

#define CE_CTRL1_SW_MASK			0x0007ffff

#define CE_CTRL1_HW_WRITE_MASK			0x00000000

#define CE_CTRL1_SW_WRITE_MASK			0x0007ffff

#define CE_CTRL1_RSTMASK			0xffffffff

#define CE_CTRL1_RESET				0x00000080



#define CE_CMD_HALT_STATUS_MSB			3

#define CE_CMD_HALT_STATUS_LSB			3

#define CE_CMD_HALT_STATUS_MASK			0x00000008

#define CE_CMD_HALT_STATUS_GET(x) \

	(((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)

#define CE_CMD_HALT_STATUS_SET(x) \

	(((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)

#define CE_CMD_HALT_STATUS_RESET		0

#define CE_CMD_HALT_MSB				0

#define CE_CMD_HALT_MASK			0x00000001



#define HOST_IE_COPY_COMPLETE_MSB		0

#define HOST_IE_COPY_COMPLETE_LSB		0

#define HOST_IE_COPY_COMPLETE_MASK		0x00000001

#define HOST_IE_COPY_COMPLETE_GET(x) \

	(((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)

#define HOST_IE_COPY_COMPLETE_SET(x) \

	(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)

#define HOST_IE_COPY_COMPLETE_RESET		0

#define HOST_IE_ADDRESS				0x002c



#define HOST_IS_DST_RING_LOW_WATERMARK_MASK	0x00000010

#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK	0x00000008

#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK	0x00000004

#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK	0x00000002

#define HOST_IS_COPY_COMPLETE_MASK		0x00000001

#define HOST_IS_ADDRESS				0x0030



#define MISC_IE_ADDRESS				0x0034



#define MISC_IS_AXI_ERR_MASK			0x00000400



#define MISC_IS_DST_ADDR_ERR_MASK		0x00000200

#define MISC_IS_SRC_LEN_ERR_MASK		0x00000100

#define MISC_IS_DST_MAX_LEN_VIO_MASK		0x00000080

#define MISC_IS_DST_RING_OVERFLOW_MASK		0x00000040

#define MISC_IS_SRC_RING_OVERFLOW_MASK		0x00000020



#define MISC_IS_ADDRESS				0x0038



#define SR_WR_INDEX_ADDRESS			0x003c



#define DST_WR_INDEX_ADDRESS			0x0040



#define CURRENT_SRRI_ADDRESS			0x0044



#define CURRENT_DRRI_ADDRESS			0x0048



#define SRC_WATERMARK_LOW_MSB			31

#define SRC_WATERMARK_LOW_LSB			16

#define SRC_WATERMARK_LOW_MASK			0xffff0000

#define SRC_WATERMARK_LOW_GET(x) \

	(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)

#define SRC_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)

#define SRC_WATERMARK_LOW_RESET			0

#define SRC_WATERMARK_HIGH_MSB			15

#define SRC_WATERMARK_HIGH_LSB			0

#define SRC_WATERMARK_HIGH_MASK			0x0000ffff

#define SRC_WATERMARK_HIGH_GET(x) \

	(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)

#define SRC_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)

#define SRC_WATERMARK_HIGH_RESET		0

#define SRC_WATERMARK_ADDRESS			0x004c



#define DST_WATERMARK_LOW_LSB			16

#define DST_WATERMARK_LOW_MASK			0xffff0000

#define DST_WATERMARK_LOW_SET(x) \

	(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)

#define DST_WATERMARK_LOW_RESET			0

#define DST_WATERMARK_HIGH_MSB			15

#define DST_WATERMARK_HIGH_LSB			0

#define DST_WATERMARK_HIGH_MASK			0x0000ffff

#define DST_WATERMARK_HIGH_GET(x) \

	(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)

#define DST_WATERMARK_HIGH_SET(x) \

	(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)

#define DST_WATERMARK_HIGH_RESET		0

#define DST_WATERMARK_ADDRESS			0x0050



static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)

{

	return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;

}



#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK  | \

			   HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \

			   HOST_IS_DST_RING_LOW_WATERMARK_MASK  | \

			   HOST_IS_DST_RING_HIGH_WATERMARK_MASK)



#define CE_ERROR_MASK	(MISC_IS_AXI_ERR_MASK           | \

			 MISC_IS_DST_ADDR_ERR_MASK      | \

			 MISC_IS_SRC_LEN_ERR_MASK       | \

			 MISC_IS_DST_MAX_LEN_VIO_MASK   | \

			 MISC_IS_DST_RING_OVERFLOW_MASK | \

			 MISC_IS_SRC_RING_OVERFLOW_MASK)



#define CE_SRC_RING_TO_DESC(baddr, idx) \

	(&(((struct ce_desc *)baddr)[idx]))

drivers/net/wireless/ath/ath10k/core.c

+50 −3
Original line number Diff line number Diff line
@@ -72,6 +72,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA9887_HW_1_0_VERSION,
@@ -93,6 +95,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA6174_HW_2_1_VERSION,
@@ -113,6 +117,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA6174_HW_2_1_VERSION,
@@ -133,6 +139,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA6174_HW_3_0_VERSION,
@@ -153,6 +161,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA6174_HW_3_2_VERSION,
@@ -176,6 +186,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.target_cpu_freq = 176000000,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA99X0_HW_2_0_DEV_VERSION,
@@ -202,6 +214,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca99x0_ops,

		.decap_align_bytes = 1,

		.spectral_bin_discard = 4,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA9984_HW_1_0_DEV_VERSION,
@@ -229,6 +243,12 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca99x0_ops,

		.decap_align_bytes = 1,

		.spectral_bin_discard = 12,



		/* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz

		 * or 2x2 160Mhz, long-guard-interval.

		 */

		.vht160_mcs_rx_highest = 1560,

		.vht160_mcs_tx_highest = 1560,

	},

	{

		.id = QCA9888_HW_2_0_DEV_VERSION,
@@ -255,6 +275,12 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca99x0_ops,

		.decap_align_bytes = 1,

		.spectral_bin_discard = 12,



		/* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or

		 * 1x1 160Mhz, long-guard-interval.

		 */

		.vht160_mcs_rx_highest = 780,

		.vht160_mcs_tx_highest = 780,

	},

	{

		.id = QCA9377_HW_1_0_DEV_VERSION,
@@ -275,6 +301,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca988x_ops,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA9377_HW_1_1_DEV_VERSION,
@@ -297,6 +325,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.target_cpu_freq = 176000000,

		.decap_align_bytes = 4,

		.spectral_bin_discard = 0,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

	{

		.id = QCA4019_HW_1_0_DEV_VERSION,
@@ -324,6 +354,8 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { 
		.hw_ops = &qca99x0_ops,

		.decap_align_bytes = 1,

		.spectral_bin_discard = 4,

		.vht160_mcs_rx_highest = 0,

		.vht160_mcs_tx_highest = 0,

	},

};
@@ -691,7 +723,7 @@ static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 
{

	u32 result, address;

	u8 board_id, chip_id;

	int ret;

	int ret, bmi_board_id_param;



	address = ar->hw_params.patch_load_addr;
@@ -715,8 +747,13 @@ static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) 
		return ret;

	}



	ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,

				 &result);

	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||

	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)

		bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;

	else

		bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;



	ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);

	if (ret) {

		ath10k_err(ar, "could not execute otp for board id check: %d\n",

			   ret);
@@ -845,6 +882,11 @@ static int ath10k_download_and_run_otp(struct ath10k *ar) 
		return ret;

	}



	/* As of now pre-cal is valid for 10_4 variants */

	if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||

	    ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE)

		bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;



	ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);

	if (ret) {

		ath10k_err(ar, "could not execute otp (%d)\n", ret);
@@ -2449,24 +2491,29 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, 
	case ATH10K_HW_QCA988X:

	case ATH10K_HW_QCA9887:

		ar->regs = &qca988x_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca988x_values;

		break;

	case ATH10K_HW_QCA6174:

	case ATH10K_HW_QCA9377:

		ar->regs = &qca6174_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca6174_values;

		break;

	case ATH10K_HW_QCA99X0:

	case ATH10K_HW_QCA9984:

		ar->regs = &qca99x0_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca99x0_values;

		break;

	case ATH10K_HW_QCA9888:

		ar->regs = &qca99x0_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca9888_values;

		break;

	case ATH10K_HW_QCA4019:

		ar->regs = &qca4019_regs;

		ar->hw_ce_regs = &qcax_ce_regs;

		ar->hw_values = &qca4019_values;

		break;

	default:

drivers/net/wireless/ath/ath10k/core.h

+1 −0
Original line number Diff line number Diff line
@@ -794,6 +794,7 @@ struct ath10k { 
	struct completion target_suspend;



	const struct ath10k_hw_regs *regs;

	const struct ath10k_hw_ce_regs *hw_ce_regs;

	const struct ath10k_hw_values *hw_values;

	struct ath10k_bmi bmi;

	struct ath10k_wmi wmi;