Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma

QCOM ADM DMA Controller

Required properties:

- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960

- reg: Address range for DMA registers

- interrupts: Should contain one interrupt shared by all channels

- #dma-cells: must be <2>.  First cell denotes the channel number.  Second cell

  denotes CRCI (client rate control interface) flow control assignment.

- clocks: Should contain the core clock and interface clock.

- clock-names: Must contain "core" for the core clock and "iface" for the

  interface clock.

- resets: Must contain an entry for each entry in reset names.

- reset-names: Must include the following entries:

  - clk

  - c0

  - c1

  - c2

- qcom,ee: indicates the security domain identifier used in the secure world.

Example:

		adm_dma: dma@18300000 {

			compatible = "qcom,adm";

			reg = <0x18300000 0x100000>;

			interrupts = <0 170 0>;

			#dma-cells = <2>;

			clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;

			clock-names = "core", "iface";

			resets = <&gcc ADM0_RESET>,

				<&gcc ADM0_C0_RESET>,

				<&gcc ADM0_C1_RESET>,

				<&gcc ADM0_C2_RESET>;

			reset-names = "clk", "c0", "c1", "c2";

			qcom,ee = <0>;

		};

DMA clients must use the format descripted in the dma.txt file, using a three

cell specifier for each channel.

Each dmas request consists of 3 cells:

 1. phandle pointing to the DMA controller

 2. channel number

 3. CRCI assignment, if applicable.  If no CRCI flow control is required, use 0.

    The CRCI is used for flow control.  It identifies the peripheral device that

    is the source/destination for the transferred data.

Example:

	spi4: spi@1a280000 {

		status = "ok";

		spi-max-frequency = <50000000>;

		pinctrl-0 = <&spi_pins>;

		pinctrl-names = "default";

		cs-gpios = <&qcom_pinmux 20 0>;

		dmas = <&adm_dma 6 9>,

			<&adm_dma 5 10>;

		dma-names = "rx", "tx";

	};

Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream

target devices. It can be configured to have one channel or two channels.

If configured as two channels, one is to transmit to the device and another

is to receive from the device.

Required properties:

- compatible: Should be "xlnx,axi-dma-1.00.a"

- #dma-cells: Should be <1>, see "dmas" property below

- reg: Should contain DMA registers location and length.

- dma-channel child node: Should have atleast one channel and can have upto

	two channels per device. This node specifies the properties of each

	DMA channel (see child node properties below).

Optional properties:

- xlnx,include-sg: Tells whether configured for Scatter-mode in

	the hardware.

Required child node properties:

- compatible: It should be either "xlnx,axi-dma-mm2s-channel" or

	"xlnx,axi-dma-s2mm-channel".

- interrupts: Should contain per channel DMA interrupts.

- xlnx,datawidth: Should contain the stream data width, take values

	{32,64...1024}.

Option child node properties:

- xlnx,include-dre: Tells whether hardware is configured for Data

	Realignment Engine.

Example:

++++++++

axi_dma_0: axidma@40400000 {

	compatible = "xlnx,axi-dma-1.00.a";

	#dma_cells = <1>;

	reg = < 0x40400000 0x10000 >;

	dma-channel@40400000 {

		compatible = "xlnx,axi-dma-mm2s-channel";

		interrupts = < 0 59 4 >;

		xlnx,datawidth = <0x40>;

	} ;

	dma-channel@40400030 {

		compatible = "xlnx,axi-dma-s2mm-channel";

		interrupts = < 0 58 4 >;

		xlnx,datawidth = <0x40>;

	} ;

} ;

* DMA client

Required properties:

- dmas: a list of <[DMA device phandle] [Channel ID]> pairs,

	where Channel ID is '0' for write/tx and '1' for read/rx

	channel.

- dma-names: a list of DMA channel names, one per "dmas" entry

Example:

++++++++

dmatest_0: dmatest@0 {

	compatible ="xlnx,axi-dma-test-1.00.a";

	dmas = <&axi_dma_0 0

		&axi_dma_0 1>;

	dma-names = "dma0", "dma1";

} ;

		unsigned long flags);

   The peripheral driver is expected to have mapped the scatterlist for

   the DMA operation prior to calling device_prep_slave_sg, and must

   the DMA operation prior to calling dmaengine_prep_slave_sg(), and must

   keep the scatterlist mapped until the DMA operation has completed.

   The scatterlist must be mapped using the DMA struct device.

   If a mapping needs to be synchronized later, dma_sync_*_for_*() must be

   Note:

	Not all DMA engine drivers can return reliable information for

	a running DMA channel.  It is recommended that DMA engine users

	pause or stop (via dmaengine_terminate_all) the channel before

	pause or stop (via dmaengine_terminate_all()) the channel before

	using this API.

M:	Viresh Kumar <viresh.linux@gmail.com>

M:	Andy Shevchenko <andriy.shevchenko@linux.intel.com>

S:	Maintained

F:	include/linux/dw_dmac.h

F:	include/linux/platform_data/dma-dw.h

F:	drivers/dma/dw/

SYNOPSYS DESIGNWARE MMC/SD/SDIO DRIVER

 */

#include <linux/clk.h>

#include <linux/delay.h>

#include <linux/dw_dmac.h>

#include <linux/platform_data/dma-dw.h>

#include <linux/fb.h>

#include <linux/init.h>

#include <linux/platform_device.h>

		goto fail;

	slave->sdata.dma_dev = &dw_dmac0_device.dev;

	slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)

				| DWC_CFGH_DST_PER(1));

	slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL

				| DWC_CFGL_HS_SRC_POL);

	slave->sdata.src_id = 0;

	slave->sdata.dst_id = 1;

	slave->sdata.src_master = 1;

	slave->sdata.dst_master = 0;

	data->dma_slave = slave;

	/* Check if DMA slave interface for capture should be configured. */

	if (flags & AC97C_CAPTURE) {

		rx_dws->dma_dev = &dw_dmac0_device.dev;

		rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);

		rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);

		rx_dws->src_id = 3;

		rx_dws->src_master = 0;

		rx_dws->dst_master = 1;

	}

	/* Check if DMA slave interface for playback should be configured. */

	if (flags & AC97C_PLAYBACK) {

		tx_dws->dma_dev = &dw_dmac0_device.dev;

		tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);

		tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);

		tx_dws->dst_id = 4;

		tx_dws->src_master = 0;

		tx_dws->dst_master = 1;

	}

	dws = &data->dws;

	dws->dma_dev = &dw_dmac0_device.dev;

	dws->cfg_hi = DWC_CFGH_DST_PER(2);

	dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);

	dws->dst_id = 2;

	dws->src_master = 0;

	dws->dst_master = 1;