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Commit 52650257 authored by Jaswinder Singh Rajput's avatar Jaswinder Singh Rajput Committed by H. Peter Anvin
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x86, mtrr: replace MTRRdefType_MSR with msr-index's MSR_MTRRdefType 



Use standard msr-index.h's MSR declaration and no need to declare again.

[ Impact: cleanup, no object code change ]

Signed-off-by: default avatarJaswinder Singh Rajput <jaswinderrajput@gmail.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent ba5673ff

arch/x86/kernel/cpu/mtrr/cleanup.c

+2 −2
Original line number Diff line number Diff line
@@ -808,7 +808,7 @@ int __init mtrr_cleanup(unsigned address_bits) 


	if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)

		return 0;

	rdmsr(MTRRdefType_MSR, def, dummy);

	rdmsr(MSR_MTRRdefType, def, dummy);

	def &= 0xff;

	if (def != MTRR_TYPE_UNCACHABLE)

		return 0;
@@ -1003,7 +1003,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn) 
	 */

	if (!is_cpu(INTEL) || disable_mtrr_trim)

		return 0;

	rdmsr(MTRRdefType_MSR, def, dummy);

	rdmsr(MSR_MTRRdefType, def, dummy);

	def &= 0xff;

	if (def != MTRR_TYPE_UNCACHABLE)

		return 0;

arch/x86/kernel/cpu/mtrr/generic.c

+4 −4
Original line number Diff line number Diff line
@@ -314,7 +314,7 @@ void __init get_mtrr_state(void) 
	if (mtrr_state.have_fixed)

		get_fixed_ranges(mtrr_state.fixed_ranges);



	rdmsr(MTRRdefType_MSR, lo, dummy);

	rdmsr(MSR_MTRRdefType, lo, dummy);

	mtrr_state.def_type = (lo & 0xff);

	mtrr_state.enabled = (lo & 0xc00) >> 10;
@@ -579,10 +579,10 @@ static void prepare_set(void) __acquires(set_atomicity_lock) 
	__flush_tlb();



	/*  Save MTRR state */

	rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);

	rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);



	/*  Disable MTRRs, and set the default type to uncached  */

	mtrr_wrmsr(MTRRdefType_MSR, deftype_lo & ~0xcff, deftype_hi);

	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);

}



static void post_set(void) __releases(set_atomicity_lock)
@@ -591,7 +591,7 @@ static void post_set(void) __releases(set_atomicity_lock) 
	__flush_tlb();



	/* Intel (P6) standard MTRRs */

	mtrr_wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);

	mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);

		

	/*  Enable caches  */

	write_cr0(read_cr0() & 0xbfffffff);

arch/x86/kernel/cpu/mtrr/mtrr.h

+0 −2
Original line number Diff line number Diff line
@@ -5,8 +5,6 @@ 
#include <linux/types.h>

#include <linux/stddef.h>



#define MTRRdefType_MSR 0x2ff



#define MTRR_CHANGE_MASK_FIXED     0x01

#define MTRR_CHANGE_MASK_VARIABLE  0x02

#define MTRR_CHANGE_MASK_DEFTYPE   0x04

arch/x86/kernel/cpu/mtrr/state.c

+3 −3
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) 


		if (use_intel())

			/*  Save MTRR state */

			rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);

			rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);

		else

			/* Cyrix ARRs - everything else were excluded at the top */

			ctxt->ccr3 = getCx86(CX86_CCR3);
@@ -46,7 +46,7 @@ void set_mtrr_cache_disable(struct set_mtrr_context *ctxt) 
{

	if (use_intel())

		/*  Disable MTRRs, and set the default type to uncached  */

		mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,

		mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,

		      ctxt->deftype_hi);

	else if (is_cpu(CYRIX))

		/* Cyrix ARRs - everything else were excluded at the top */
@@ -64,7 +64,7 @@ void set_mtrr_done(struct set_mtrr_context *ctxt) 
		/*  Restore MTRRdefType  */

		if (use_intel())

			/* Intel (P6) standard MTRRs */

			mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);

			mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);

		else

			/* Cyrix ARRs - everything else was excluded at the top */

			setCx86(CX86_CCR3, ctxt->ccr3);