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Commit 519c31ba authored by Joerg Roedel's avatar Joerg Roedel Committed by Ingo Molnar
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x86, AMD IOMMU: use status bit instead of memory write-back for completion wait



Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent b635acec
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+10 −7
Original line number Diff line number Diff line
@@ -101,16 +101,13 @@ static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
 */
static int iommu_completion_wait(struct amd_iommu *iommu)
{
	int ret;
	int ret, ready = 0;
	unsigned status = 0;
	struct iommu_cmd cmd;
	volatile u64 ready = 0;
	unsigned long ready_phys = virt_to_phys(&ready);
	unsigned long i = 0;

	memset(&cmd, 0, sizeof(cmd));
	cmd.data[0] = LOW_U32(ready_phys) | CMD_COMPL_WAIT_STORE_MASK;
	cmd.data[1] = upper_32_bits(ready_phys);
	cmd.data[2] = 1; /* value written to 'ready' */
	cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
	CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);

	iommu->need_sync = 0;
@@ -122,9 +119,15 @@ static int iommu_completion_wait(struct amd_iommu *iommu)

	while (!ready && (i < EXIT_LOOP_COUNT)) {
		++i;
		cpu_relax();
		/* wait for the bit to become one */
		status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
		ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
	}

	/* set bit back to zero */
	status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
	writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);

	if (unlikely((i == EXIT_LOOP_COUNT) && printk_ratelimit()))
		printk(KERN_WARNING "AMD IOMMU: Completion wait loop failed\n");

+4 −0
Original line number Diff line number Diff line
@@ -69,6 +69,9 @@
#define MMIO_EVT_TAIL_OFFSET	0x2018
#define MMIO_STATUS_OFFSET	0x2020

/* MMIO status bits */
#define MMIO_STATUS_COM_WAIT_INT_MASK	0x04

/* feature control bits */
#define CONTROL_IOMMU_EN        0x00ULL
#define CONTROL_HT_TUN_EN       0x01ULL
@@ -89,6 +92,7 @@
#define CMD_INV_IOMMU_PAGES     0x03

#define CMD_COMPL_WAIT_STORE_MASK	0x01
#define CMD_COMPL_WAIT_INT_MASK		0x02
#define CMD_INV_IOMMU_PAGES_SIZE_MASK	0x01
#define CMD_INV_IOMMU_PAGES_PDE_MASK	0x02