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Commit 50b76e4b authored by Deepak Kumar's avatar Deepak Kumar
Browse files

msm: kgsl: Track RSCC sleep sequence state 



RSCC wake-up sequence should only be triggered if RSCC
sleep sequence was done earlier i.e. they should always
be balanced to make sure GMU FW, RSCC and PDC state are
in sync.

Add GMU_RSCC_SLEEP_SEQ_DONE GMU flag to track whether
RSCC sleep sequence was done or not and trigger sleep
and wake-up sequence based on this flag to make they
are always balanced.

Change-Id: I78d8be52a770bd6e939da91fa68b6fd01f10034e
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent d2b4b6f2

drivers/gpu/msm/adreno_a6xx_gmu.c

+12 −3
Original line number Diff line number Diff line
@@ -319,6 +319,10 @@ static int a6xx_rpmh_power_on_gpu(struct kgsl_device *device) 
	struct device *dev = &gmu->pdev->dev;

	int val;



	/* Only trigger wakeup sequence if sleep sequence was done earlier */

	if (!test_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags))

		return 0;



	kgsl_gmu_regread(device, A6XX_GPU_CC_GX_DOMAIN_MISC, &val);

	if (!(val & 0x1))

		dev_err_ratelimited(&gmu->pdev->dev,
@@ -348,6 +352,9 @@ static int a6xx_rpmh_power_on_gpu(struct kgsl_device *device) 


	kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 0);



	/* Clear sleep sequence flag as wakeup sequence is successful */

	clear_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags);



	/* Enable the power counter because it was disabled before slumber */

	kgsl_gmu_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
@@ -363,6 +370,9 @@ static int a6xx_rpmh_power_off_gpu(struct kgsl_device *device) 
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	int ret;



	if (test_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags))

		return 0;



	/* RSC sleep sequence is different on v1 */

	if (adreno_is_a630v1(adreno_dev))

		kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1);
@@ -405,6 +415,7 @@ static int a6xx_rpmh_power_off_gpu(struct kgsl_device *device) 
			test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

		kgsl_gmu_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 0);



	set_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags);

	return 0;

}
@@ -851,15 +862,13 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device, 
	unsigned int chipid = 0;



	switch (boot_state) {

	case GMU_RESET:

		/* fall through */

	case GMU_COLD_BOOT:

		/* Turn on TCM retention */

		kgsl_gmu_regwrite(device, A6XX_GMU_GENERAL_7, 1);



		if (!test_and_set_bit(GMU_BOOT_INIT_DONE, &gmu->flags))

			_load_gmu_rpmh_ucode(device);

		else if (boot_state != GMU_RESET) {

		else {

			ret = a6xx_rpmh_power_on_gpu(device);

			if (ret)

				return ret;

drivers/gpu/msm/kgsl_gmu.c

+2 −2
Original line number Diff line number Diff line
@@ -1729,7 +1729,7 @@ int gmu_start(struct kgsl_device *device) 
			gmu_irq_enable(device);



			ret = gpudev->rpmh_gpu_pwrctrl(

				adreno_dev, GMU_FW_START, GMU_RESET, 0);

				adreno_dev, GMU_FW_START, GMU_COLD_BOOT, 0);

			if (ret)

				goto error_gmu;
@@ -1746,7 +1746,7 @@ int gmu_start(struct kgsl_device *device) 
			hfi_stop(gmu);



			ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_START,

					GMU_RESET, 0);

					GMU_COLD_BOOT, 0);

			if (ret)

				goto error_gmu;

drivers/gpu/msm/kgsl_gmu.h

+2 −3
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ enum gmu_flags { 
	GMU_DCVS_REPLAY,

	GMU_GPMU,

	GMU_ENABLED,

	GMU_RSCC_SLEEP_SEQ_DONE,

};



/**
@@ -136,13 +137,11 @@ struct rpmh_votes_t { 


/*

 * These are the different ways the GMU can boot. GMU_WARM_BOOT is waking up

 * from slumber. GMU_COLD_BOOT is booting for the first time. GMU_RESET

 * is a soft reset of the GMU.

 * from slumber. GMU_COLD_BOOT is booting for the first time.

 */

enum gmu_boot {

	GMU_WARM_BOOT = 0,

	GMU_COLD_BOOT = 1,

	GMU_RESET = 2

};



enum gmu_load_mode {