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Commit 50a0bc90 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make INTEL_DEVID only take dev_priv 



Saves 4472 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent c1812bdb

drivers/gpu/drm/i915/i915_drv.c

+8 −6
Original line number Diff line number Diff line
@@ -188,12 +188,14 @@ static void intel_detect_pch(struct drm_device *dev) 
				dev_priv->pch_type = PCH_LPT;

				DRM_DEBUG_KMS("Found LynxPoint PCH\n");

				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));

				WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));

				WARN_ON(IS_HSW_ULT(dev_priv) ||

					IS_BDW_ULT(dev_priv));

			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_LPT;

				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");

				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));

				WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));

				WARN_ON(!IS_HSW_ULT(dev_priv) &&

					!IS_BDW_ULT(dev_priv));

			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {

				dev_priv->pch_type = PCH_SPT;

				DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
@@ -422,7 +424,7 @@ intel_setup_mchbar(struct drm_device *dev) 


	dev_priv->mchbar_need_disable = false;



	if (IS_I915G(dev) || IS_I915GM(dev)) {

	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);

		enabled = !!(temp & DEVEN_MCHBAR_EN);

	} else {
@@ -440,7 +442,7 @@ intel_setup_mchbar(struct drm_device *dev) 
	dev_priv->mchbar_need_disable = true;



	/* Space is allocated or reserved, so enable it. */

	if (IS_I915G(dev) || IS_I915GM(dev)) {

	if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,

				       temp | DEVEN_MCHBAR_EN);

	} else {
@@ -456,7 +458,7 @@ intel_teardown_mchbar(struct drm_device *dev) 
	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;



	if (dev_priv->mchbar_need_disable) {

		if (IS_I915G(dev) || IS_I915GM(dev)) {

		if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {

			u32 deven_val;



			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
@@ -1053,7 +1055,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 
	 * be lost or delayed, but we use them anyways to avoid

	 * stuck interrupts on some machines.

	 */

	if (!IS_I945G(dev) && !IS_I945GM(dev)) {

	if (!IS_I945G(dev_priv) && !IS_I945GM(dev_priv)) {

		if (pci_enable_msi(pdev) < 0)

			DRM_DEBUG_DRIVER("can't enable MSI");

	}

drivers/gpu/drm/i915/i915_drv.h

+57 −54
Original line number Diff line number Diff line
@@ -2601,7 +2601,8 @@ struct drm_i915_cmd_table { 
})

#define INTEL_INFO(p)	(&__I915__(p)->info)

#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)

#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)



#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)



#define REVID_FOREVER		0xff

#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
@@ -2633,27 +2634,27 @@ struct drm_i915_cmd_table { 
#define IS_REVID(p, since, until) \

	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))



#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)

#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)

#define IS_I830(dev_priv)	(INTEL_DEVID(dev_priv) == 0x3577)

#define IS_845G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2562)

#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)

#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)

#define IS_I865G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2572)

#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)

#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)

#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)

#define IS_I915GM(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2592)

#define IS_I945G(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2772)

#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)

#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)

#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)

#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)

#define IS_GM45(dev_priv)	(INTEL_DEVID(dev_priv) == 0x2A42)

#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)

#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)

#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)

#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)

#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)

#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)

#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)

#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)

#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)

#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)

#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \

				 INTEL_DEVID(dev) == 0x0152 || \

				 INTEL_DEVID(dev) == 0x015a)

#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \

				 INTEL_DEVID(dev_priv) == 0x0152 || \

				 INTEL_DEVID(dev_priv) == 0x015a)

#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)

#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)

#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
@@ -2662,44 +2663,44 @@ struct drm_i915_cmd_table { 
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)

#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)

#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)

#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \

				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)

#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \

				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\

				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\

				 (INTEL_DEVID(dev) & 0xf) == 0xe))

#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \

				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)

#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \

				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\

				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\

				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))

/* ULX machines are also considered ULT. */

#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \

				 (INTEL_DEVID(dev) & 0xf) == 0xe)

#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)

#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \

				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)

#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)

#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)

#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)

#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

/* ULX machines are also considered ULT. */

#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \

				 INTEL_DEVID(dev) == 0x0A1E)

#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \

				 INTEL_DEVID(dev) == 0x1913 || \

				 INTEL_DEVID(dev) == 0x1916 || \

				 INTEL_DEVID(dev) == 0x1921 || \

				 INTEL_DEVID(dev) == 0x1926)

#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \

				 INTEL_DEVID(dev) == 0x1915 || \

				 INTEL_DEVID(dev) == 0x191E)

#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \

				 INTEL_DEVID(dev) == 0x5913 || \

				 INTEL_DEVID(dev) == 0x5916 || \

				 INTEL_DEVID(dev) == 0x5921 || \

				 INTEL_DEVID(dev) == 0x5926)

#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \

				 INTEL_DEVID(dev) == 0x5915 || \

				 INTEL_DEVID(dev) == 0x591E)

#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)

#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \

				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \

				 INTEL_DEVID(dev_priv) == 0x0A1E)

#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \

				 INTEL_DEVID(dev_priv) == 0x1913 || \

				 INTEL_DEVID(dev_priv) == 0x1916 || \

				 INTEL_DEVID(dev_priv) == 0x1921 || \

				 INTEL_DEVID(dev_priv) == 0x1926)

#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \

				 INTEL_DEVID(dev_priv) == 0x1915 || \

				 INTEL_DEVID(dev_priv) == 0x191E)

#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \

				 INTEL_DEVID(dev_priv) == 0x5913 || \

				 INTEL_DEVID(dev_priv) == 0x5916 || \

				 INTEL_DEVID(dev_priv) == 0x5921 || \

				 INTEL_DEVID(dev_priv) == 0x5926)

#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \

				 INTEL_DEVID(dev_priv) == 0x5915 || \

				 INTEL_DEVID(dev_priv) == 0x591E)

#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)

#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \

				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)



#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@ -2778,7 +2779,7 @@ struct drm_i915_cmd_table { 
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)



/* Early gen2 have a totally busted CS tlb and require pinned batches. */

#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))

#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_845G(dev_priv))



/* WaRsDisableCoarsePowerGating:skl,bxt */

#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
@@ -2798,8 +2799,9 @@ struct drm_i915_cmd_table { 
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte

 * rows, which changed the alignment requirements and fence programming.

 */

#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \

						      IS_I915GM(dev)))

#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \

					 !(IS_I915G(dev_priv) || \

					 IS_I915GM(dev_priv)))

#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)

#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
@@ -2807,7 +2809,7 @@ struct drm_i915_cmd_table { 
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)

#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)



#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))

#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))



#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
@@ -2863,7 +2865,8 @@ struct drm_i915_cmd_table { 


/* DPF == dynamic parity feature */

#define HAS_L3_DPF(dev) (INTEL_INFO(dev)->has_l3_dpf)

#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))

#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \

				 2 : HAS_L3_DPF(dev_priv))



#define GT_FREQUENCY_MULTIPLIER 50

#define GEN9_FREQ_SCALER 3

drivers/gpu/drm/i915/i915_gem.c

+17 −19
Original line number Diff line number Diff line
@@ -4388,30 +4388,28 @@ void i915_gem_init_swizzling(struct drm_device *dev) 
		BUG();

}



static void init_unused_ring(struct drm_device *dev, u32 base)

static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base)

{

	struct drm_i915_private *dev_priv = to_i915(dev);



	I915_WRITE(RING_CTL(base), 0);

	I915_WRITE(RING_HEAD(base), 0);

	I915_WRITE(RING_TAIL(base), 0);

	I915_WRITE(RING_START(base), 0);

}



static void init_unused_rings(struct drm_device *dev)

static void init_unused_rings(struct drm_i915_private *dev_priv)

{

	if (IS_I830(dev)) {

		init_unused_ring(dev, PRB1_BASE);

		init_unused_ring(dev, SRB0_BASE);

		init_unused_ring(dev, SRB1_BASE);

		init_unused_ring(dev, SRB2_BASE);

		init_unused_ring(dev, SRB3_BASE);

	} else if (IS_GEN2(dev)) {

		init_unused_ring(dev, SRB0_BASE);

		init_unused_ring(dev, SRB1_BASE);

	} else if (IS_GEN3(dev)) {

		init_unused_ring(dev, PRB1_BASE);

		init_unused_ring(dev, PRB2_BASE);

	if (IS_I830(dev_priv)) {

		init_unused_ring(dev_priv, PRB1_BASE);

		init_unused_ring(dev_priv, SRB0_BASE);

		init_unused_ring(dev_priv, SRB1_BASE);

		init_unused_ring(dev_priv, SRB2_BASE);

		init_unused_ring(dev_priv, SRB3_BASE);

	} else if (IS_GEN2(dev_priv)) {

		init_unused_ring(dev_priv, SRB0_BASE);

		init_unused_ring(dev_priv, SRB1_BASE);

	} else if (IS_GEN3(dev_priv)) {

		init_unused_ring(dev_priv, PRB1_BASE);

		init_unused_ring(dev_priv, PRB2_BASE);

	}

}
@@ -4430,7 +4428,7 @@ i915_gem_init_hw(struct drm_device *dev) 
		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));



	if (IS_HASWELL(dev))

		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?

		I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?

			   LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);



	if (HAS_PCH_NOP(dev_priv)) {
@@ -4453,7 +4451,7 @@ i915_gem_init_hw(struct drm_device *dev) 
	 * will prevent c3 entry. Makes sure all unused rings

	 * are totally idle.

	 */

	init_unused_rings(dev);

	init_unused_rings(dev_priv);



	BUG_ON(!dev_priv->kernel_context);

drivers/gpu/drm/i915/i915_gem_stolen.c

+3 −3
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
		pci_read_config_dword(pdev, INTEL_BSM, &bsm);



		base = bsm & INTEL_BSM_MASK;

	} else if (IS_I865G(dev)) {

	} else if (IS_I865G(dev_priv)) {

		u32 tseg_size = 0;

		u16 toud = 0;

		u8 tmp;
@@ -154,7 +154,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
		tom = tmp * MB(32);



		base = tom - tseg_size - ggtt->stolen_size;

	} else if (IS_845G(dev)) {

	} else if (IS_845G(dev_priv)) {

		u32 tseg_size = 0;

		u32 tom;

		u8 tmp;
@@ -178,7 +178,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
		tom = tmp * MB(32);



		base = tom - tseg_size - ggtt->stolen_size;

	} else if (IS_I830(dev)) {

	} else if (IS_I830(dev_priv)) {

		u32 tseg_size = 0;

		u32 tom;

		u8 tmp;

drivers/gpu/drm/i915/i915_gem_tiling.c

+2 −1
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
static bool

i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)

{

	struct drm_i915_private *dev_priv = to_i915(dev);

	int tile_width;



	/* Linear is always fine */
@@ -72,7 +73,7 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 
		return false;



	if (IS_GEN2(dev) ||

	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))

	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev_priv)))

		tile_width = 128;

	else

		tile_width = 512;