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Commit 5084e93d authored by Jayachandran C's avatar Jayachandran C Committed by Ralf Baechle
Browse files

MIPS: Netlogic: Handle XLP hardware errata 



Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: default avatarJayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8902/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b3b73ae6

arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h

+2 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
#define CPU_BLOCKID_FPU		9

#define CPU_BLOCKID_MAP		10



#define IFU_BRUB_RESERVE	0x007



#define ICU_DEFEATURE		0x100



#define LSU_DEFEATURE		0x304

arch/mips/netlogic/common/reset.S

+20 −0
Original line number Diff line number Diff line
@@ -235,6 +235,26 @@ EXPORT(nlm_boot_siblings) 
	mfc0	v0, CP0_EBASE, 1

	andi	v0, 0x3ff		/* v0 <- node/core */



	/*

	 * Errata: to avoid potential live lock, setup IFU_BRUB_RESERVE

	 * when running 4 threads per core

	 */

	andi	v1, v0, 0x3             /* v1 <- thread id */

	bnez	v1, 2f

	nop



	/* thread 0 of each core. */

	li	t0, CKSEG1ADDR(RESET_DATA_PHYS)

	lw	t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */

	subu	t1, 0x3				/* 4-thread per core mode? */

	bnez	t1, 2f

	nop



	li	t0, IFU_BRUB_RESERVE

	li	t1, 0x55

	mtcr	t1, t0

	_ehb

2:

	beqz	v0, 4f		/* boot cpu (cpuid == 0)? */

	nop