Loading arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -262,7 +262,7 @@ "pcie_tbu_clk", "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; resets = <&clock_gcc GCC_PCIE_0_BCR>, Loading Loading @@ -552,7 +552,7 @@ "pcie_tbu_clk", "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; resets = <&clock_gcc GCC_PCIE_1_BCR>, Loading Loading
arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi +2 −2 Original line number Diff line number Diff line Loading @@ -262,7 +262,7 @@ "pcie_tbu_clk", "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; resets = <&clock_gcc GCC_PCIE_0_BCR>, Loading Loading @@ -552,7 +552,7 @@ "pcie_tbu_clk", "pcie_phy_refgen_clk", "pcie_phy_aux_clk"; max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>, <0>, <0>, <100000000>, <0>; resets = <&clock_gcc GCC_PCIE_1_BCR>, Loading