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Commit 4f193e8b authored by Hareesh Gundu's avatar Hareesh Gundu
Browse files

msm: kgsl: Do not access GMU_HFI_ON flag in power control 



HFI is not a common feature, it's specific to few A6xx GPUs.
Move HFI flags related operations inside GMU module.

Change-Id: I3041533854389514c6737b167dd5c4b521886924
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
parent cba91098

drivers/gpu/msm/kgsl_gmu.c

+17 −1
Original line number Diff line number Diff line
@@ -609,6 +609,18 @@ static int gmu_dcvs_set(struct kgsl_device *device, 
		.bw = INVALID_DCVS_IDX,

	};



	/* Do not set to XO and lower GPU clock vote from GMU */

	if ((gpu_pwrlevel != INVALID_DCVS_IDX) &&

			(gpu_pwrlevel >= gmu->num_gpupwrlevels - 1))

		return -EINVAL;



	/* If GMU has not been started, save it */

	if (!test_bit(GMU_HFI_ON, &device->gmu_core.flags)) {

		/* store clock change request */

		set_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags);

		return 0;

	}



	if (gpu_pwrlevel < gmu->num_gpupwrlevels - 1)

		req.freq = gmu->num_gpupwrlevels - gpu_pwrlevel - 1;
@@ -617,8 +629,10 @@ static int gmu_dcvs_set(struct kgsl_device *device, 


	/* GMU will vote for slumber levels through the sleep sequence */

	if ((req.freq == INVALID_DCVS_IDX) &&

		(req.bw == INVALID_DCVS_IDX))

		(req.bw == INVALID_DCVS_IDX)) {

		clear_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags);

		return 0;

	}



	if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG))

		ret = gmu_dev_ops->rpmh_gpu_pwrctrl(adreno_dev,
@@ -635,6 +649,8 @@ static int gmu_dcvs_set(struct kgsl_device *device, 
		adreno_dispatcher_schedule(device);

	}



	/* indicate actual clock change */

	clear_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags);

	return ret;

}

drivers/gpu/msm/kgsl_pwrctrl.c

+2 −21
Original line number Diff line number Diff line
@@ -251,28 +251,9 @@ int kgsl_clk_set_rate(struct kgsl_device *device, 
	int ret = 0;



	/* GMU scales GPU freq */

	if (gmu_core_gpmu_isenabled(device)) {

		int num_gpupwrlevels = pwr->num_pwrlevels;



		/* If GMU has not been started, save it */

		if (!test_bit(GMU_HFI_ON, &device->gmu_core.flags)) {

			/* store clock change request */

			set_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags);

			return 0;

		}



		if (num_gpupwrlevels < 0)

			return -EINVAL;



		/* If the GMU is on we cannot vote for the lowest level */

		if (pwrlevel == (num_gpupwrlevels - 1)) {

			WARN(1, "Cannot set 0 GPU frequency with GMU\n");

			return -EINVAL;

		}

	if (gmu_core_gpmu_isenabled(device))

		ret = gmu_core_dcvs_set(device, pwrlevel, INVALID_DCVS_IDX);

		/* indicate actual clock change */

		clear_bit(GMU_DCVS_REPLAY, &device->gmu_core.flags);

	} else

	else

		/* Linux clock driver scales GPU freq */

		ret = kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],

			pl->gpu_freq, clocks[0]);