Loading arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +21 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,14 @@ qcom,skip-init; qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk"; #size-cells = <1>; #address-cells = <1>; ranges; Loading Loading @@ -168,3 +176,16 @@ iommus = <&apps_smmu 0x21 0>; }; }; &kgsl_smmu { qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x3ff 0x303>; }; &apps_smmu { qcom,actlr = /* MMRT and MMNRT TBUs: +3 deep PF */ <0x400 0x3ff 0x103>, <0x800 0x3ff 0x103>; }; Loading
arch/arm64/boot/dts/qcom/msm-arm-smmu-trinket.dtsi +21 −0 Original line number Diff line number Diff line Loading @@ -24,6 +24,14 @@ qcom,skip-init; qcom,use-3-lvl-tables; #global-interrupts = <1>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>, <&clock_gpucc GPU_CC_AHB_CLK>; clock-names = "gcc_gpu_memnoc_gfx_clk", "gcc_gpu_snoc_dvm_gfx_clk", "gpu_cc_ahb_clk"; #size-cells = <1>; #address-cells = <1>; ranges; Loading Loading @@ -168,3 +176,16 @@ iommus = <&apps_smmu 0x21 0>; }; }; &kgsl_smmu { qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x3ff 0x303>; }; &apps_smmu { qcom,actlr = /* MMRT and MMNRT TBUs: +3 deep PF */ <0x400 0x3ff 0x103>, <0x800 0x3ff 0x103>; };