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Commit 4e1f224d authored by Jeevan Shriram's avatar Jeevan Shriram
Browse files

ARM: dts: msm: Add L1 cache definitions to sdmshrike target 



Ad L1 I/D cache nodes and cpu dump nodes for sdmshrike target.

Change-Id: I0381321dc83983812b1cb8f4084c23eb482a653e
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
parent 8c3a7f09

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+164 −0
Original line number Diff line number Diff line
@@ -59,6 +59,16 @@ 
				      cache-level = <3>;

				};

			};



			L1_I_0: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};



			L1_D_0: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};



		CPU1: cpu@100 {
@@ -74,6 +84,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_100: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};



			L1_D_100: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};



		CPU2: cpu@200 {
@@ -89,6 +109,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_200: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};



			L1_D_200: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};



		CPU3: cpu@300 {
@@ -104,6 +134,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_300: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};



			L1_D_300: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0xa000>;

			};

		};



		CPU4: cpu@400 {
@@ -119,6 +159,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_400: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};



			L1_D_400: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};



		CPU5: cpu@500 {
@@ -134,6 +184,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_500: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};



			L1_D_500: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};



		CPU6: cpu@600 {
@@ -149,6 +209,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_600: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};



			L1_D_600: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};



		CPU7: cpu@700 {
@@ -164,6 +234,16 @@ 
			      cache-level = <2>;

			      next-level-cache = <&L3_0>;

			};



			L1_I_700: l1-icache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};



			L1_D_700: l1-dcache {

				compatible = "arm,arch-cache";

				qcom,dump-size = <0x14000>;

			};

		};



		cpu-map {
@@ -210,6 +290,90 @@ 
		};

	};



	cpuss_dump {

		compatible = "qcom,cpuss-dump";



		qcom,l1_i_cache0 {

			qcom,dump-node = <&L1_I_0>;

			qcom,dump-id = <0x60>;

		};



		qcom,l1_i_cache1 {

			qcom,dump-node = <&L1_I_100>;

			qcom,dump-id = <0x61>;

		};



		qcom,l1_i_cache2 {

			qcom,dump-node = <&L1_I_200>;

			qcom,dump-id = <0x62>;

		};



		qcom,l1_i_cache3 {

			qcom,dump-node = <&L1_I_300>;

			qcom,dump-id = <0x63>;

		};



		qcom,l1_i_cache100 {

			qcom,dump-node = <&L1_I_400>;

			qcom,dump-id = <0x64>;

		};



		qcom,l1_i_cache101 {

			qcom,dump-node = <&L1_I_500>;

			qcom,dump-id = <0x65>;

		};



		qcom,l1_i_cache102 {

			qcom,dump-node = <&L1_I_600>;

			qcom,dump-id = <0x66>;

		};



		qcom,l1_i_cache103 {

			qcom,dump-node = <&L1_I_700>;

			qcom,dump-id = <0x67>;

		};



		qcom,l1_d_cache0 {

			qcom,dump-node = <&L1_D_0>;

			qcom,dump-id = <0x80>;

		};



		qcom,l1_d_cache1 {

			qcom,dump-node = <&L1_D_100>;

			qcom,dump-id = <0x81>;

		};



		qcom,l1_d_cache2 {

			qcom,dump-node = <&L1_D_200>;

			qcom,dump-id = <0x82>;

		};



		qcom,l1_d_cache3 {

			qcom,dump-node = <&L1_D_300>;

			qcom,dump-id = <0x83>;

		};



		qcom,l1_d_cache100 {

			qcom,dump-node = <&L1_D_400>;

			qcom,dump-id = <0x84>;

		};



		qcom,l1_d_cache101 {

			qcom,dump-node = <&L1_D_500>;

			qcom,dump-id = <0x85>;

		};



		qcom,l1_d_cache102 {

			qcom,dump-node = <&L1_D_600>;

			qcom,dump-id = <0x86>;

		};



		qcom,l1_d_cache103 {

			qcom,dump-node = <&L1_D_700>;

			qcom,dump-id = <0x87>;

		};

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;