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Commit 4dd3594d authored by Linux Build Service Account's avatar Linux Build Service Account
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Merge a487c3ab on remote branch 

Change-Id: If22a4107aa2c5033710021eb19252f1a34ad72c2
parents d04ffc87 a487c3ab

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ stable kernels. 
| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

Documentation/devicetree/bindings/qseecom/qseecom.txt

+3 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ Optional properties: 
  - qcom,qsee-reentrancy-support: indicates the qsee reentrancy phase supported by the target

  - qcom,commonlib64-loaded-by-uefi: indicates commonlib64 is loaded by uefi already

  - qcom,fde-key-size: indicates which FDE key size is used in device.

  - qcom,enable-key-wrap-in-ks: enables wrapping of ICE key with KS key.



Example:

	qcom,qseecom@fe806000 {
@@ -40,6 +41,7 @@ Example: 
		qcom,hlos-ce-hw-instance = <1 2>;

		qcom,qsee-ce-hw-instance = <0>;

		qcom,support-fde;

		qcom,enable-key-wrap-in-ks;

		qcom,support-pfe;

		qcom,msm_bus,name = "qseecom-noc";

		qcom,msm_bus,num_cases = <4>;
@@ -64,6 +66,7 @@ Example: The following dts setup is the same as the example above. 
		reg = <0x7f00000 0x500000>;

		reg-names = "secapp-region";

		qcom,support-fde;

		qcom,enable-key-wrap-in-ks;

		qcom,full-disk-encrypt-info = <0 1 2>, <0 2 2>;

		qcom,support-pfe;

		qcom,per-file-encrypt-info = <0 1 0>, <0 2 0>;

arch/arm/configs/vendor/sdxprairie-perf_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -185,6 +185,7 @@ CONFIG_TUN=y 
CONFIG_KS8851=y

# CONFIG_NET_VENDOR_MICROCHIP is not set

# CONFIG_NET_VENDOR_NATSEMI is not set

CONFIG_RMNET=y

# CONFIG_NET_VENDOR_SEEQ is not set

# CONFIG_NET_VENDOR_SMSC is not set

# CONFIG_NET_VENDOR_STMICRO is not set
@@ -223,6 +224,7 @@ CONFIG_THERMAL=y 
CONFIG_QCOM_SPMI_TEMP_ALARM=y

CONFIG_MFD_SPMI_PMIC=y

CONFIG_REGULATOR=y

CONFIG_REGULATOR_RPMH=y

CONFIG_REGULATOR_STUB=y

CONFIG_SOUND=y

CONFIG_SND=y

arch/arm/configs/vendor/sdxprairie_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ CONFIG_TUN=y 
CONFIG_KS8851=y

# CONFIG_NET_VENDOR_MICROCHIP is not set

# CONFIG_NET_VENDOR_NATSEMI is not set

CONFIG_RMNET=y

# CONFIG_NET_VENDOR_SEEQ is not set

# CONFIG_NET_VENDOR_SMSC is not set

# CONFIG_NET_VENDOR_STMICRO is not set
@@ -214,6 +215,7 @@ CONFIG_THERMAL=y 
CONFIG_QCOM_SPMI_TEMP_ALARM=y

CONFIG_MFD_SPMI_PMIC=y

CONFIG_REGULATOR=y

CONFIG_REGULATOR_RPMH=y

CONFIG_REGULATOR_STUB=y

CONFIG_FB=y

CONFIG_SOUND=y

arch/arm64/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -506,6 +506,24 @@ config ARM64_ERRATUM_1024718 


	  If unsure, say Y.



config ARM64_ERRATUM_1286807

	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"

	default y

	select ARM64_WORKAROUND_REPEAT_TLBI

	help

	  This option adds workaround for ARM Cortex-A76 erratum 1286807



	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual

	  address for a cacheable mapping of a location is being

	  accessed by a core while another core is remapping the virtual

	  address to a new physical page using the recommended

	  break-before-make sequence, then under very rare circumstances

	  TLBI+DSB completes before a read using the translation being

	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y
@@ -575,9 +593,16 @@ config QCOM_FALKOR_ERRATUM_1003 
	  is unchanged. Work around the erratum by invalidating the walk cache

	  entries for the trampoline before entering the kernel proper.



config ARM64_WORKAROUND_REPEAT_TLBI

	bool

	help

	  Enable the repeat TLBI workaround for Falkor erratum 1009 and

	  Cortex-A76 erratum 1286807.



config QCOM_FALKOR_ERRATUM_1009

	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"

	default y

	select ARM64_WORKAROUND_REPEAT_TLBI

	help

	  On Falkor v1, the CPU may prematurely complete a DSB following a

	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation