Merge "ARM: dts: msm: add smmu devices for trinket"

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

	kgsl_smmu: kgsl-smmu@0x59a0000 {

		status = "disabled";

		compatible = "qcom,qsmmu-v500";

		reg = <0x59a0000 0x10000>,

			<0x59c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,dynamic;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

		gfx_0_tbu: gfx_0_tbu@0x59c5000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0x59c5000 0x1000>,

				<0x59c2200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};

	};

	apps_smmu: apps-smmu@0xc600000 {

		status = "disabled";

		compatible = "qcom,qsmmu-v500";

		reg = <0xc600000 0x80000>,

			<0xc782000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

		anoc_1_tbu: anoc_1_tbu@0xc785000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0xc785000 0x1000>,

				<0xc782200 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x0 0x400>;

		};

		mm_rt_tbu: mm_rt_tbu@0xc789000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0xc789000 0x1000>,

				<0xc782208 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x400 0x400>;

		};

		mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0xc78d000 0x1000>,

				<0xc782210 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0x800 0x400>;

		};

		cdsp_tbu: cdsp_tbu@0xc791000 {

			compatible = "qcom,qsmmuv500-tbu";

			reg = <0xc791000 0x1000>,

				<0xc782218 0x8>;

			reg-names = "base", "status-reg";

			qcom,stream-id-range = <0xc00 0x400>;

		};

	};

};

#include "trinket-regulator.dtsi"

#include "trinket-gdsc.dtsi"

#include "trinket-usb.dtsi"

#include "msm-arm-smmu-trinket.dtsi"

&ufs_phy_gdsc {

	status = "ok";