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Commit 4c2880b3 authored by Jon Hunter's avatar Jon Hunter Committed by Thomas Gleixner
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irqchip/gic: Ensure gic_cpu_if_up/down() programs correct GIC instance 



Commit 32289506 ("irqchip: gic: Preserve gic V2 bypass bits in cpu
ctrl register") added a new function, gic_cpu_if_up(), to program the
GIC CPU_CTRL register. This function assumes that there is only one GIC
instance present and hence always uses the chip data for the primary GIC
controller. Although it is not common for there to be a secondary, some
devices do support a secondary. Therefore, fix this by passing
gic_cpu_if_up() a pointer to the appropriate chip data structure.

Similarly, the function gic_cpu_if_down() only assumes that there is a
single GIC instance present. Update this function so that an instance
number is passed for the appropriate GIC and return an error code on
failure. The vexpress TC2 (which has a single GIC) is currently the only
user of this function and so update it accordingly. Note that because the
TC2 only has a single GIC, the call to gic_cpu_if_down() should always
be successful.

Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1438332252-25248-2-git-send-email-jonathanh@nvidia.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 567e5a01

arch/arm/mach-vexpress/tc2_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static void tc2_pm_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) 
	 * to the CPU by disabling the GIC CPU IF to prevent wfi

	 * from completing execution behind power controller back

	 */

	gic_cpu_if_down();

	gic_cpu_if_down(0);

}



static void tc2_pm_cluster_powerdown_prepare(unsigned int cluster)

drivers/irqchip/irq-gic.c

+12 −6
Original line number Diff line number Diff line
@@ -356,9 +356,9 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic) 
	return mask;

}



static void gic_cpu_if_up(void)

static void gic_cpu_if_up(struct gic_chip_data *gic)

{

	void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);

	void __iomem *cpu_base = gic_data_cpu_base(gic);

	u32 bypass = 0;



	/*
@@ -426,17 +426,23 @@ static void gic_cpu_init(struct gic_chip_data *gic) 
	gic_cpu_config(dist_base, NULL);



	writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);

	gic_cpu_if_up();

	gic_cpu_if_up(gic);

}



void gic_cpu_if_down(void)

int gic_cpu_if_down(unsigned int gic_nr)

{

	void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);

	void __iomem *cpu_base;

	u32 val = 0;



	if (gic_nr >= MAX_GIC_NR)

		return -EINVAL;



	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);

	val = readl(cpu_base + GIC_CPU_CTRL);

	val &= ~GICC_ENABLE;

	writel_relaxed(val, cpu_base + GIC_CPU_CTRL);



	return 0;

}



#ifdef CONFIG_CPU_PM
@@ -572,7 +578,7 @@ static void gic_cpu_restore(unsigned int gic_nr) 
					dist_base + GIC_DIST_PRI + i * 4);



	writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);

	gic_cpu_if_up();

	gic_cpu_if_up(&gic_data[gic_nr]);

}



static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)

include/linux/irqchip/arm-gic.h

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ struct device_node; 
void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,

		    u32 offset, struct device_node *);

void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);

void gic_cpu_if_down(void);

int gic_cpu_if_down(unsigned int gic_nr);



static inline void gic_init(unsigned int nr, int start,

			    void __iomem *dist , void __iomem *cpu)