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Commit 4bf58283 authored by Fuad Hossain's avatar Fuad Hossain
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drm/msm/sde: reset ctl path registers when wb encoder disabled 



In MDP 5.0, when the wb encoder is disabled, the
control path must be reset. This change uses the
same reset logic already used in the video
encoder. The existing reset logic is modified to
take care of writeback. The reset logic for each
phys encoder is moved to a single helper function
where possible. If there is a cdm block attached
to the physical encoder that is being disabled,
it is now unbinded from the pingpong block. The
control flush bits are now set using the ops APIs
instead of hardcoding them in the post disable
function.

Change-Id: I5cc8668d10b7192d4822964ec2feadcf1b50d925
Signed-off-by: default avatarFuad Hossain <fhossain@codeaurora.org>
parent 0bb81cfe

drivers/gpu/drm/msm/sde/sde_encoder.c

+66 −0
Original line number Diff line number Diff line
@@ -3177,6 +3177,72 @@ static void sde_encoder_virt_disable(struct drm_encoder *drm_enc) 
	sde_rm_release(&sde_kms->rm, drm_enc);

}



void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,

		struct sde_encoder_phys_wb *wb_enc)

{

	struct sde_encoder_virt *sde_enc;



	if (wb_enc) {

		if (sde_encoder_helper_reset_mixers(phys_enc,

				wb_enc->fb_disable))

			return;



		if (wb_enc->hw_wb->ops.bind_pingpong_blk) {

			wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,

					false, phys_enc->hw_pp->idx);



			if (phys_enc->hw_ctl->ops.update_bitmask_wb)

				phys_enc->hw_ctl->ops.update_bitmask_wb(

						phys_enc->hw_ctl,

						wb_enc->hw_wb->idx, true);

		}

	} else {

		if (phys_enc->hw_intf->ops.bind_pingpong_blk) {

			phys_enc->hw_intf->ops.bind_pingpong_blk(

					phys_enc->hw_intf, false,

					phys_enc->hw_pp->idx);



			if (phys_enc->hw_ctl->ops.update_bitmask_intf)

				phys_enc->hw_ctl->ops.update_bitmask_intf(

						phys_enc->hw_ctl,

						phys_enc->hw_intf->idx, true);

		}

	}



	if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {

		phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);



		if (phys_enc->hw_ctl->ops.update_bitmask_merge3d &&

				phys_enc->hw_pp->merge_3d)

			phys_enc->hw_ctl->ops.update_bitmask_merge3d(

					phys_enc->hw_ctl,

					phys_enc->hw_pp->merge_3d->idx, true);

	}



	if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&

			phys_enc->hw_pp) {

		phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,

				false, phys_enc->hw_pp->idx);



		if (phys_enc->hw_ctl->ops.update_bitmask_cdm)

			phys_enc->hw_ctl->ops.update_bitmask_cdm(

					phys_enc->hw_ctl,

					phys_enc->hw_cdm->idx, true);

	}



	sde_enc = to_sde_encoder_virt(phys_enc->parent);



	if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&

			phys_enc->hw_pp->merge_3d &&

			phys_enc->hw_ctl->ops.reset_post_disable)

		phys_enc->hw_ctl->ops.reset_post_disable(

				phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,

				phys_enc->hw_pp->merge_3d->idx);



	phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);

	phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);

}



static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,

		enum sde_intf_type type, u32 controller_id)

{

drivers/gpu/drm/msm/sde/sde_encoder_phys.h

+9 −0
Original line number Diff line number Diff line
@@ -695,4 +695,13 @@ static inline bool sde_encoder_phys_needs_single_flush( 
			(_sde_encoder_phys_is_ppsplit(phys_enc) ||

				_sde_encoder_phys_is_dual_ctl(phys_enc));

}



/**

 * sde_encoder_helper_phys_disable - helper function to disable virt encoder

 * @phys_enc: Pointer to physical encoder structure

 * @wb_enc: Pointer to writeback encoder structure

 */

void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,

		struct sde_encoder_phys_wb *wb_enc);



#endif /* __sde_encoder_phys_H__ */

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+1 −13
Original line number Diff line number Diff line
@@ -1122,19 +1122,7 @@ static void sde_encoder_phys_vid_disable(struct sde_encoder_phys *phys_enc) 
		sde_encoder_phys_vid_control_vblank_irq(phys_enc, false);

	}



	if (phys_enc->hw_intf->ops.bind_pingpong_blk)

		phys_enc->hw_intf->ops.bind_pingpong_blk(phys_enc->hw_intf,

				false, phys_enc->hw_pp->idx - PINGPONG_0);



	if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode)

		phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);



	if (phys_enc->hw_pp && phys_enc->hw_pp->merge_3d &&

			phys_enc->hw_ctl->ops.reset_post_te_disable)

		phys_enc->hw_ctl->ops.reset_post_te_disable(

				phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,

				phys_enc->hw_pp->merge_3d->idx);



	sde_encoder_helper_phys_disable(phys_enc, NULL);

exit:

	SDE_EVT32(DRMID(phys_enc->parent),

		atomic_read(&phys_enc->pending_retire_fence_cnt));

drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c

+8 −2
Original line number Diff line number Diff line
@@ -1547,13 +1547,19 @@ static void sde_encoder_phys_wb_disable(struct sde_encoder_phys *phys_enc) 
	/* reset h/w before final flush */

	if (phys_enc->hw_ctl->ops.clear_pending_flush)

		phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);

	if (sde_encoder_helper_reset_mixers(phys_enc, wb_enc->fb_disable))

		goto exit;



	sde_encoder_helper_phys_disable(phys_enc, wb_enc);



	phys_enc->enable_state = SDE_ENC_DISABLING;



	if (hw_wb->catalog->has_3d_merge_reset)

		goto exit;



	sde_encoder_phys_wb_prepare_for_kickoff(phys_enc, NULL);



	if (phys_enc->hw_ctl->ops.trigger_flush)

		phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);



	sde_encoder_helper_trigger_start(phys_enc);

	sde_encoder_phys_wb_wait_for_commit_done(phys_enc);

exit:

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -3604,6 +3604,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->sui_ns_allowed = true;

		sde_cfg->sui_misr_supported = true;

		sde_cfg->sui_block_xin_mask = 0x3F71;

		sde_cfg->has_3d_merge_reset = true;

	} else if (IS_SDMSHRIKE_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 24;