Loading arch/mips/kernel/smtc.c +29 −29 Original line number Original line Diff line number Diff line Loading @@ -582,8 +582,8 @@ void smtc_init_secondary(void) * SMTC init code assigns TCs consdecutively and in ascending order * SMTC init code assigns TCs consdecutively and in ascending order * to across available VPEs. * to across available VPEs. */ */ if(((read_c0_tcbind() & TCBIND_CURTC) != 0) if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && && ((read_c0_tcbind() & TCBIND_CURVPE) ((read_c0_tcbind() & TCBIND_CURVPE) != cpu_data[smp_processor_id() - 1].vpe_id)){ != cpu_data[smp_processor_id() - 1].vpe_id)){ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); } } Loading Loading
arch/mips/kernel/smtc.c +29 −29 Original line number Original line Diff line number Diff line Loading @@ -582,8 +582,8 @@ void smtc_init_secondary(void) * SMTC init code assigns TCs consdecutively and in ascending order * SMTC init code assigns TCs consdecutively and in ascending order * to across available VPEs. * to across available VPEs. */ */ if(((read_c0_tcbind() & TCBIND_CURTC) != 0) if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && && ((read_c0_tcbind() & TCBIND_CURVPE) ((read_c0_tcbind() & TCBIND_CURVPE) != cpu_data[smp_processor_id() - 1].vpe_id)){ != cpu_data[smp_processor_id() - 1].vpe_id)){ write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); } } Loading