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Commit 4be460d9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Not too much this time.

   - One nouveau workaround extended to a few more GPUs
   - Some amdgpu big endian fixes, and a regression fixer
   - Some vmwgfx fixes
   - One ttm locking fix
   - One vgaarb fix"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  vgaarb: fix signal handling in vga_get()
  radeon: Fix VCE IB test on Big-Endian systems
  radeon: Fix VCE ring test for Big-Endian systems
  radeon/cik: Fix GFX IB test on Big-Endian
  drm/amdgpu: fix the lost duplicates checking
  drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by default
  drm/vmwgfx: Implement the cursor_set2 callback v2
  drm/vmwgfx: fix a warning message
  drm/ttm: Fixed a read/write lock imbalance
parents 0bd0f1e6 9f5bd308

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+8 −0
Original line number Original line Diff line number Diff line
@@ -477,6 +477,14 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 
		if (domain == AMDGPU_GEM_DOMAIN_CPU)

		if (domain == AMDGPU_GEM_DOMAIN_CPU)

			goto error_unreserve;

			goto error_unreserve;

	}

	}

	list_for_each_entry(entry, &duplicates, head) {

		domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type);

		/* if anything is swapped out don't swap it in here,

		   just abort and wait for the next CS */

		if (domain == AMDGPU_GEM_DOMAIN_CPU)

			goto error_unreserve;

	}



	r = amdgpu_vm_update_page_directory(adev, bo_va->vm);

	r = amdgpu_vm_update_page_directory(adev, bo_va->vm);

	if (r)

	if (r)

		goto error_unreserve;

		goto error_unreserve;

drivers/gpu/drm/nouveau/include/nvkm/core/device.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -159,7 +159,6 @@ struct nvkm_device_func { 
struct nvkm_device_quirk {

struct nvkm_device_quirk {

	u8 tv_pin_mask;

	u8 tv_pin_mask;

	u8 tv_gpio;

	u8 tv_gpio;

	bool War00C800_0;

};

};





struct nvkm_device_chip {

struct nvkm_device_chip {

drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c

+4 −31
Original line number Original line Diff line number Diff line
@@ -258,12 +258,6 @@ nvkm_device_pci_10de_0df4[] = { 
	{}

	{}

};

};





static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_0fcd[] = {

	{ 0x17aa, 0x3801, NULL, { .War00C800_0 = true } }, /* Lenovo Y510P */

	{}

};



static const struct nvkm_device_pci_vendor

static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_0fd2[] = {

nvkm_device_pci_10de_0fd2[] = {

	{ 0x1028, 0x0595, "GeForce GT 640M LE" },

	{ 0x1028, 0x0595, "GeForce GT 640M LE" },
@@ -278,12 +272,6 @@ nvkm_device_pci_10de_0fe3[] = { 
	{}

	{}

};

};





static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_0fe4[] = {

	{ 0x144d, 0xc740, NULL, { .War00C800_0 = true } },

	{}

};



static const struct nvkm_device_pci_vendor

static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_104b[] = {

nvkm_device_pci_10de_104b[] = {

	{ 0x1043, 0x844c, "GeForce GT 625" },

	{ 0x1043, 0x844c, "GeForce GT 625" },
@@ -690,13 +678,6 @@ nvkm_device_pci_10de_1189[] = { 
static const struct nvkm_device_pci_vendor

static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_1199[] = {

nvkm_device_pci_10de_1199[] = {

	{ 0x1458, 0xd001, "GeForce GTX 760" },

	{ 0x1458, 0xd001, "GeForce GTX 760" },

	{ 0x1462, 0x1106, "GeForce GTX 780M", { .War00C800_0 = true } }, /* Medion Erazer X7827 */

	{}

};



static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_11e0[] = {

	{ 0x1558, 0x5106, NULL, { .War00C800_0 = true } },

	{}

	{}

};

};
@@ -706,14 +687,6 @@ nvkm_device_pci_10de_11e3[] = { 
	{}

	{}

};

};





static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_11fc[] = {

	{ 0x1179, 0x0001, NULL, { .War00C800_0 = true } }, /* Toshiba Tecra W50 */

	{ 0x17aa, 0x2211, NULL, { .War00C800_0 = true } }, /* Lenovo W541 */

	{ 0x17aa, 0x221e, NULL, { .War00C800_0 = true } }, /* Lenovo W541 */

	{}

};



static const struct nvkm_device_pci_vendor

static const struct nvkm_device_pci_vendor

nvkm_device_pci_10de_1247[] = {

nvkm_device_pci_10de_1247[] = {

	{ 0x1043, 0x212a, "GeForce GT 635M" },

	{ 0x1043, 0x212a, "GeForce GT 635M" },
@@ -1368,7 +1341,7 @@ nvkm_device_pci_10de[] = { 
	{ 0x0fc6, "GeForce GTX 650" },

	{ 0x0fc6, "GeForce GTX 650" },

	{ 0x0fc8, "GeForce GT 740" },

	{ 0x0fc8, "GeForce GT 740" },

	{ 0x0fc9, "GeForce GT 730" },

	{ 0x0fc9, "GeForce GT 730" },

	{ 0x0fcd, "GeForce GT 755M", nvkm_device_pci_10de_0fcd },

	{ 0x0fcd, "GeForce GT 755M" },

	{ 0x0fce, "GeForce GT 640M LE" },

	{ 0x0fce, "GeForce GT 640M LE" },

	{ 0x0fd1, "GeForce GT 650M" },

	{ 0x0fd1, "GeForce GT 650M" },

	{ 0x0fd2, "GeForce GT 640M", nvkm_device_pci_10de_0fd2 },

	{ 0x0fd2, "GeForce GT 640M", nvkm_device_pci_10de_0fd2 },
@@ -1382,7 +1355,7 @@ nvkm_device_pci_10de[] = { 
	{ 0x0fe1, "GeForce GT 730M" },

	{ 0x0fe1, "GeForce GT 730M" },

	{ 0x0fe2, "GeForce GT 745M" },

	{ 0x0fe2, "GeForce GT 745M" },

	{ 0x0fe3, "GeForce GT 745M", nvkm_device_pci_10de_0fe3 },

	{ 0x0fe3, "GeForce GT 745M", nvkm_device_pci_10de_0fe3 },

	{ 0x0fe4, "GeForce GT 750M", nvkm_device_pci_10de_0fe4 },

	{ 0x0fe4, "GeForce GT 750M" },

	{ 0x0fe9, "GeForce GT 750M" },

	{ 0x0fe9, "GeForce GT 750M" },

	{ 0x0fea, "GeForce GT 755M" },

	{ 0x0fea, "GeForce GT 755M" },

	{ 0x0fec, "GeForce 710A" },

	{ 0x0fec, "GeForce 710A" },
@@ -1497,12 +1470,12 @@ nvkm_device_pci_10de[] = { 
	{ 0x11c6, "GeForce GTX 650 Ti" },

	{ 0x11c6, "GeForce GTX 650 Ti" },

	{ 0x11c8, "GeForce GTX 650" },

	{ 0x11c8, "GeForce GTX 650" },

	{ 0x11cb, "GeForce GT 740" },

	{ 0x11cb, "GeForce GT 740" },

	{ 0x11e0, "GeForce GTX 770M", nvkm_device_pci_10de_11e0 },

	{ 0x11e0, "GeForce GTX 770M" },

	{ 0x11e1, "GeForce GTX 765M" },

	{ 0x11e1, "GeForce GTX 765M" },

	{ 0x11e2, "GeForce GTX 765M" },

	{ 0x11e2, "GeForce GTX 765M" },

	{ 0x11e3, "GeForce GTX 760M", nvkm_device_pci_10de_11e3 },

	{ 0x11e3, "GeForce GTX 760M", nvkm_device_pci_10de_11e3 },

	{ 0x11fa, "Quadro K4000" },

	{ 0x11fa, "Quadro K4000" },

	{ 0x11fc, "Quadro K2100M", nvkm_device_pci_10de_11fc },

	{ 0x11fc, "Quadro K2100M" },

	{ 0x1200, "GeForce GTX 560 Ti" },

	{ 0x1200, "GeForce GTX 560 Ti" },

	{ 0x1201, "GeForce GTX 560" },

	{ 0x1201, "GeForce GTX 560" },

	{ 0x1203, "GeForce GTX 460 SE v2" },

	{ 0x1203, "GeForce GTX 460 SE v2" },

drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c

+1 −3
Original line number Original line Diff line number Diff line
@@ -81,9 +81,7 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable) 
	nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);

	nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);

	nvkm_rd32(device, 0x000200);

	nvkm_rd32(device, 0x000200);





	if ( nvkm_boolopt(device->cfgopt, "War00C800_0",

	if (nvkm_boolopt(device->cfgopt, "War00C800_0", true)) {

	    device->quirk ? device->quirk->War00C800_0 : false)) {

		nvkm_info(&pmu->subdev, "hw bug workaround enabled\n");

		switch (device->chipset) {

		switch (device->chipset) {

		case 0xe4:

		case 0xe4:

			magic(device, 0x04000000);

			magic(device, 0x04000000);

drivers/gpu/drm/radeon/cik.c

+1 −5
Original line number Original line Diff line number Diff line
@@ -4173,11 +4173,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 
	control |= ib->length_dw | (vm_id << 24);

	control |= ib->length_dw | (vm_id << 24);





	radeon_ring_write(ring, header);

	radeon_ring_write(ring, header);

	radeon_ring_write(ring,

	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC));

#ifdef __BIG_ENDIAN

			  (2 << 0) |

#endif

			  (ib->gpu_addr & 0xFFFFFFFC));

	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);

	radeon_ring_write(ring, control);

	radeon_ring_write(ring, control);

}

}