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Commit 4bdcc4ea authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/amdgpu: coding style refine in sdma_v4_0.c 



Replace 8 spaces with tabs.
correct {} braces, etc.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 79690b84

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+75 −76
Original line number Diff line number Diff line
@@ -48,8 +48,7 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 
static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev);

static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev);



static const u32 golden_settings_sdma_4[] =

{

static const u32 golden_settings_sdma_4[] = {

	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CHICKEN_BITS), 0xfe931f07, 0x02831f07,

	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), 0xff000ff0, 0x3f000100,

	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_IB_CNTL), 0x800f0100, 0x00000100,
@@ -76,8 +75,7 @@ static const u32 golden_settings_sdma_4[] = 
	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_UTCL1_PAGE), 0x000003ff, 0x000003c0

};



static const u32 golden_settings_sdma_vg10[] =

{

static const u32 golden_settings_sdma_vg10[] = {

	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,

	SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 0x00104002,

	SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG), 0x0018773f, 0x00104002,
@@ -87,6 +85,7 @@ static const u32 golden_settings_sdma_vg10[] = 
static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)

{

	u32 base = 0;



	switch (instance) {

	case 0:

		base = SDMA0_BASE.instance[0].segment[0];
@@ -159,7 +158,8 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 
	case CHIP_VEGA10:

		chip_name = "vega10";

		break;

	default: BUG();

	default:

		BUG();

	}



	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -192,9 +192,7 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 
	}

out:

	if (err) {

		printk(KERN_ERR

		       "sdma_v4_0: Failed to load firmware \"%s\"\n",

		       fw_name);

		DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name);

		for (i = 0; i < adev->sdma.num_instances; i++) {

			release_firmware(adev->sdma.instance[i].fw);

			adev->sdma.instance[i].fw = NULL;
@@ -243,6 +241,7 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 
	} else {

		u32 lowbit, highbit;

		int me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;



		wptr = &local_wptr;

		lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) >> 2;

		highbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
@@ -285,6 +284,7 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 
		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);

	} else {

		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;



		DRM_DEBUG("Not using doorbell -- "

				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "

				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
@@ -694,9 +694,7 @@ static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 




		for (j = 0; j < fw_size; j++)

		{

			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

		}



		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

	}
@@ -795,9 +793,8 @@ static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 


	for (i = 0; i < adev->usec_timeout; i++) {

		tmp = le32_to_cpu(adev->wb.wb[index]);

		if (tmp == 0xDEADBEEF) {

		if (tmp == 0xDEADBEEF)

			break;

		}

		DRM_UDELAY(1);

	}
@@ -1191,8 +1188,10 @@ static bool sdma_v4_0_is_idle(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	u32 i;



	for (i = 0; i < adev->sdma.num_instances; i++) {

		u32 tmp = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_STATUS_REG));



		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))

			return false;

	}
@@ -1205,6 +1204,7 @@ static int sdma_v4_0_wait_for_idle(void *handle) 
	unsigned i;

	u32 sdma0, sdma1;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	for (i = 0; i < adev->usec_timeout; i++) {

		sdma0 = RREG32(sdma_v4_0_get_reg_offset(0, mmSDMA0_STATUS_REG));

		sdma1 = RREG32(sdma_v4_0_get_reg_offset(1, mmSDMA0_STATUS_REG));
@@ -1599,8 +1599,7 @@ static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 
	}

}



const struct amdgpu_ip_block_version sdma_v4_0_ip_block =

{

const struct amdgpu_ip_block_version sdma_v4_0_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_SDMA,

	.major = 4,

	.minor = 0,