Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +12 −1 Original line number Diff line number Diff line Loading @@ -3608,6 +3608,17 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; } else if (IS_SM6150_TARGET(hw_rev)) { sde_cfg->has_cwb_support = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x2EE3; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading @@ -3626,7 +3637,7 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, if (!sde_cfg) return -EINVAL; if (IS_SM8150_TARGET(hw_rev)) { if (IS_SM8150_TARGET(hw_rev) || IS_SM6150_TARGET(hw_rev)) { sde_cfg->sui_supported_blendstage = sde_cfg->max_mixer_blendstages - SDE_STAGE_0; Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,7 @@ #define SDE_HW_VER_500 SDE_HW_VER(5, 0, 0) /* sm8150 v1.0 */ #define SDE_HW_VER_501 SDE_HW_VER(5, 0, 1) /* sm8150 v2.0 */ #define SDE_HW_VER_510 SDE_HW_VER(5, 1, 0) /* sdmshrike v1.0 */ #define SDE_HW_VER_530 SDE_HW_VER(5, 3, 0) /* sm6150 v1.0 */ #define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300) Loading @@ -60,6 +61,7 @@ #define IS_SDM670_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_410) #define IS_SM8150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_500) #define IS_SDMSHRIKE_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_510) #define IS_SM6150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_530) #define SDE_HW_BLK_NAME_LEN 16 Loading drivers/gpu/drm/msm/sde/sde_hw_lm.c +2 −1 Original line number Diff line number Diff line Loading @@ -264,7 +264,8 @@ static void _setup_mixer_ops(struct sde_mdss_cfg *m, ops->setup_mixer_out = sde_hw_lm_setup_out; if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion) || IS_SM8150_TARGET(m->hwversion) || IS_SDMSHRIKE_TARGET(m->hwversion)) IS_SDMSHRIKE_TARGET(m->hwversion) || IS_SM6150_TARGET(m->hwversion)) ops->setup_blend_config = sde_hw_lm_setup_blend_config_sdm845; else ops->setup_blend_config = sde_hw_lm_setup_blend_config; Loading drivers/gpu/drm/msm/sde/sde_hw_vbif.c +1 −1 Original line number Diff line number Diff line Loading @@ -241,7 +241,7 @@ static void _setup_vbif_ops(const struct sde_mdss_cfg *m, ops->get_halt_ctrl = sde_hw_get_halt_ctrl; if (test_bit(SDE_VBIF_QOS_REMAP, &cap)) ops->set_qos_remap = sde_hw_set_qos_remap; if (IS_SM8150_TARGET(m->hwversion)) if (IS_SM8150_TARGET(m->hwversion) || IS_SM6150_TARGET(m->hwversion)) ops->set_mem_type = sde_hw_set_mem_type_v1; else ops->set_mem_type = sde_hw_set_mem_type; Loading drivers/gpu/drm/msm/sde_dbg.c +1 −1 Original line number Diff line number Diff line Loading @@ -4998,7 +4998,7 @@ void sde_dbg_init_dbg_buses(u32 hwversion) dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998; dbg->dbgbus_vbif_rt.cmn.entries_size = ARRAY_SIZE(vbif_dbg_bus_msm8998); } else if (IS_SM8150_TARGET(hwversion)) { } else if (IS_SM8150_TARGET(hwversion) || IS_SM6150_TARGET(hwversion)) { dbg->dbgbus_sde.entries = dbg_bus_sde_sm8150; dbg->dbgbus_sde.cmn.entries_size = ARRAY_SIZE(dbg_bus_sde_sm8150); Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +12 −1 Original line number Diff line number Diff line Loading @@ -3608,6 +3608,17 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; } else if (IS_SM6150_TARGET(hw_rev)) { sde_cfg->has_cwb_support = true; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x2EE3; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading @@ -3626,7 +3637,7 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg, if (!sde_cfg) return -EINVAL; if (IS_SM8150_TARGET(hw_rev)) { if (IS_SM8150_TARGET(hw_rev) || IS_SM6150_TARGET(hw_rev)) { sde_cfg->sui_supported_blendstage = sde_cfg->max_mixer_blendstages - SDE_STAGE_0; Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -53,6 +53,7 @@ #define SDE_HW_VER_500 SDE_HW_VER(5, 0, 0) /* sm8150 v1.0 */ #define SDE_HW_VER_501 SDE_HW_VER(5, 0, 1) /* sm8150 v2.0 */ #define SDE_HW_VER_510 SDE_HW_VER(5, 1, 0) /* sdmshrike v1.0 */ #define SDE_HW_VER_530 SDE_HW_VER(5, 3, 0) /* sm6150 v1.0 */ #define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300) Loading @@ -60,6 +61,7 @@ #define IS_SDM670_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_410) #define IS_SM8150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_500) #define IS_SDMSHRIKE_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_510) #define IS_SM6150_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_530) #define SDE_HW_BLK_NAME_LEN 16 Loading
drivers/gpu/drm/msm/sde/sde_hw_lm.c +2 −1 Original line number Diff line number Diff line Loading @@ -264,7 +264,8 @@ static void _setup_mixer_ops(struct sde_mdss_cfg *m, ops->setup_mixer_out = sde_hw_lm_setup_out; if (IS_SDM845_TARGET(m->hwversion) || IS_SDM670_TARGET(m->hwversion) || IS_SM8150_TARGET(m->hwversion) || IS_SDMSHRIKE_TARGET(m->hwversion)) IS_SDMSHRIKE_TARGET(m->hwversion) || IS_SM6150_TARGET(m->hwversion)) ops->setup_blend_config = sde_hw_lm_setup_blend_config_sdm845; else ops->setup_blend_config = sde_hw_lm_setup_blend_config; Loading
drivers/gpu/drm/msm/sde/sde_hw_vbif.c +1 −1 Original line number Diff line number Diff line Loading @@ -241,7 +241,7 @@ static void _setup_vbif_ops(const struct sde_mdss_cfg *m, ops->get_halt_ctrl = sde_hw_get_halt_ctrl; if (test_bit(SDE_VBIF_QOS_REMAP, &cap)) ops->set_qos_remap = sde_hw_set_qos_remap; if (IS_SM8150_TARGET(m->hwversion)) if (IS_SM8150_TARGET(m->hwversion) || IS_SM6150_TARGET(m->hwversion)) ops->set_mem_type = sde_hw_set_mem_type_v1; else ops->set_mem_type = sde_hw_set_mem_type; Loading
drivers/gpu/drm/msm/sde_dbg.c +1 −1 Original line number Diff line number Diff line Loading @@ -4998,7 +4998,7 @@ void sde_dbg_init_dbg_buses(u32 hwversion) dbg->dbgbus_vbif_rt.entries = vbif_dbg_bus_msm8998; dbg->dbgbus_vbif_rt.cmn.entries_size = ARRAY_SIZE(vbif_dbg_bus_msm8998); } else if (IS_SM8150_TARGET(hwversion)) { } else if (IS_SM8150_TARGET(hwversion) || IS_SM6150_TARGET(hwversion)) { dbg->dbgbus_sde.entries = dbg_bus_sde_sm8150; dbg->dbgbus_sde.cmn.entries_size = ARRAY_SIZE(dbg_bus_sde_sm8150); Loading