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Commit 4b52416a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx5-fixes' 



Saeed Mahameed says:

====================
Mellanox 100G mlx5 fixes 28-12-2016

Some fixes for mlx5 core and ethernet driver.

for -stable:
    net/mlx5: Check FW limitations on log_max_qp before setting it
    net/mlx5: Cancel recovery work in remove flow
    net/mlx5: Avoid shadowing numa_node
    net/mlx5: Mask destination mac value in ethtool steering rules
    net/mlx5: Prevent setting multicast macs for VFs
    net/mlx5e: Don't sync netdev state when not registered
    net/mlx5e: Disable netdev after close
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 0df0f207 37f304d1

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c

+3 −0
Original line number Diff line number Diff line
@@ -723,6 +723,9 @@ static void mlx5e_ets_init(struct mlx5e_priv *priv) 
	int i;

	struct ieee_ets ets;



	if (!MLX5_CAP_GEN(priv->mdev, ets))

		return;



	memset(&ets, 0, sizeof(ets));

	ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;

	for (i = 0; i < ets.ets_cap; i++) {

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+0 −17
Original line number Diff line number Diff line
@@ -171,7 +171,6 @@ static int mlx5e_get_sset_count(struct net_device *dev, int sset) 
		return NUM_SW_COUNTERS +

		       MLX5E_NUM_Q_CNTRS(priv) +

		       NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +

		       NUM_PCIE_COUNTERS +

		       MLX5E_NUM_RQ_STATS(priv) +

		       MLX5E_NUM_SQ_STATS(priv) +

		       MLX5E_NUM_PFC_COUNTERS(priv) +
@@ -219,14 +218,6 @@ static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data) 
		strcpy(data + (idx++) * ETH_GSTRING_LEN,

		       pport_2819_stats_desc[i].format);



	for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)

		strcpy(data + (idx++) * ETH_GSTRING_LEN,

		       pcie_perf_stats_desc[i].format);



	for (i = 0; i < NUM_PCIE_TAS_COUNTERS; i++)

		strcpy(data + (idx++) * ETH_GSTRING_LEN,

		       pcie_tas_stats_desc[i].format);



	for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {

		for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)

			sprintf(data + (idx++) * ETH_GSTRING_LEN,
@@ -339,14 +330,6 @@ static void mlx5e_get_ethtool_stats(struct net_device *dev, 
		data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,

						  pport_2819_stats_desc, i);



	for (i = 0; i < NUM_PCIE_PERF_COUNTERS; i++)

		data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,

						  pcie_perf_stats_desc, i);



	for (i = 0; i < NUM_PCIE_TAS_COUNTERS; i++)

		data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_tas_counters,

						  pcie_tas_stats_desc, i);



	for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {

		for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)

			data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],

drivers/net/ethernet/mellanox/mlx5/core/en_fs_ethtool.c

+1 −0
Original line number Diff line number Diff line
@@ -247,6 +247,7 @@ static int set_flow_attrs(u32 *match_c, u32 *match_v, 
	}

	if (fs->flow_type & FLOW_MAC_EXT &&

	    !is_zero_ether_addr(fs->m_ext.h_dest)) {

		mask_spec(fs->m_ext.h_dest, fs->h_ext.h_dest, ETH_ALEN);

		ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4,

					     outer_headers_c, dmac_47_16),

				fs->m_ext.h_dest);

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+16 −35
Original line number Diff line number Diff line
@@ -291,36 +291,12 @@ static void mlx5e_update_q_counter(struct mlx5e_priv *priv) 
				      &qcnt->rx_out_of_buffer);

}



static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)

{

	struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;

	struct mlx5_core_dev *mdev = priv->mdev;

	int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);

	void *out;

	u32 *in;



	in = mlx5_vzalloc(sz);

	if (!in)

		return;



	out = pcie_stats->pcie_perf_counters;

	MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);

	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);



	out = pcie_stats->pcie_tas_counters;

	MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);

	mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);



	kvfree(in);

}



void mlx5e_update_stats(struct mlx5e_priv *priv)

{

	mlx5e_update_q_counter(priv);

	mlx5e_update_vport_counters(priv);

	mlx5e_update_pport_counters(priv);

	mlx5e_update_sw_counters(priv);

	mlx5e_update_pcie_counters(priv);

}



void mlx5e_update_stats_work(struct work_struct *work)
@@ -3805,14 +3781,7 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv) 


	mlx5_lag_add(mdev, netdev);



	if (mlx5e_vxlan_allowed(mdev)) {

		rtnl_lock();

		udp_tunnel_get_rx_info(netdev);

		rtnl_unlock();

	}



	mlx5e_enable_async_events(priv);

	queue_work(priv->wq, &priv->set_rx_mode_work);



	if (MLX5_CAP_GEN(mdev, vport_group_manager)) {

		mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
@@ -3822,6 +3791,18 @@ static void mlx5e_nic_enable(struct mlx5e_priv *priv) 
		rep.netdev = netdev;

		mlx5_eswitch_register_vport_rep(esw, 0, &rep);

	}



	if (netdev->reg_state != NETREG_REGISTERED)

		return;



	/* Device already registered: sync netdev system state */

	if (mlx5e_vxlan_allowed(mdev)) {

		rtnl_lock();

		udp_tunnel_get_rx_info(netdev);

		rtnl_unlock();

	}



	queue_work(priv->wq, &priv->set_rx_mode_work);

}



static void mlx5e_nic_disable(struct mlx5e_priv *priv)
@@ -3966,10 +3947,6 @@ void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev) 
	const struct mlx5e_profile *profile = priv->profile;



	set_bit(MLX5E_STATE_DESTROYING, &priv->state);

	if (profile->disable)

		profile->disable(priv);



	flush_workqueue(priv->wq);



	rtnl_lock();

	if (netif_running(netdev))
@@ -3977,6 +3954,10 @@ void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev) 
	netif_device_detach(netdev);

	rtnl_unlock();



	if (profile->disable)

		profile->disable(priv);

	flush_workqueue(priv->wq);



	mlx5e_destroy_q_counter(priv);

	profile->cleanup_rx(priv);

	mlx5e_close_drop_rq(priv);

drivers/net/ethernet/mellanox/mlx5/core/en_stats.h

+1 −31
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \

	(*(u32 *)((char *)ptr + dsc[i].offset))

#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \

	be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))

	be64_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))



#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)

#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
@@ -276,32 +276,6 @@ static const struct counter_desc pport_per_prio_pfc_stats_desc[] = { 
	{ "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },

};



#define PCIE_PERF_OFF(c) \

	MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)

#define PCIE_PERF_GET(pcie_stats, c) \

	MLX5_GET(mpcnt_reg, pcie_stats->pcie_perf_counters, \

		 counter_set.pcie_perf_cntrs_grp_data_layout.c)

#define PCIE_TAS_OFF(c) \

	MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_tas_cntrs_grp_data_layout.c)

#define PCIE_TAS_GET(pcie_stats, c) \

	MLX5_GET(mpcnt_reg, pcie_stats->pcie_tas_counters, \

		 counter_set.pcie_tas_cntrs_grp_data_layout.c)



struct mlx5e_pcie_stats {

	__be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];

	__be64 pcie_tas_counters[MLX5_ST_SZ_QW(mpcnt_reg)];

};



static const struct counter_desc pcie_perf_stats_desc[] = {

	{ "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },

	{ "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },

};



static const struct counter_desc pcie_tas_stats_desc[] = {

	{ "tx_pci_transport_nonfatal_msg", PCIE_TAS_OFF(non_fatal_err_msg_sent) },

	{ "tx_pci_transport_fatal_msg", PCIE_TAS_OFF(fatal_err_msg_sent) },

};



struct mlx5e_rq_stats {

	u64 packets;

	u64 bytes;
@@ -386,8 +360,6 @@ static const struct counter_desc sq_stats_desc[] = { 
#define NUM_PPORT_802_3_COUNTERS	ARRAY_SIZE(pport_802_3_stats_desc)

#define NUM_PPORT_2863_COUNTERS		ARRAY_SIZE(pport_2863_stats_desc)

#define NUM_PPORT_2819_COUNTERS		ARRAY_SIZE(pport_2819_stats_desc)

#define NUM_PCIE_PERF_COUNTERS		ARRAY_SIZE(pcie_perf_stats_desc)

#define NUM_PCIE_TAS_COUNTERS		ARRAY_SIZE(pcie_tas_stats_desc)

#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \

	ARRAY_SIZE(pport_per_prio_traffic_stats_desc)

#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
@@ -397,7 +369,6 @@ static const struct counter_desc sq_stats_desc[] = { 
					 NUM_PPORT_2819_COUNTERS  + \

					 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \

					 NUM_PPORT_PRIO)

#define NUM_PCIE_COUNTERS		(NUM_PCIE_PERF_COUNTERS + NUM_PCIE_TAS_COUNTERS)

#define NUM_RQ_STATS			ARRAY_SIZE(rq_stats_desc)

#define NUM_SQ_STATS			ARRAY_SIZE(sq_stats_desc)
@@ -406,7 +377,6 @@ struct mlx5e_stats { 
	struct mlx5e_qcounter_stats qcnt;

	struct mlx5e_vport_stats vport;

	struct mlx5e_pport_stats pport;

	struct mlx5e_pcie_stats pcie;

	struct rtnl_link_stats64 vf_vport;

};