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Commit 4b319b9f authored by Chris Redpath's avatar Chris Redpath
Browse files

ANDROID: arm64, dts: add hikey cpu capacity-dmips-mhz information 



Hikey is an SMP platform, so this property would normally not be necessary.

But since we drive the setting of the EAS specific sched domain flag
SD_SHARE_CAP_STATES via the init_cpu_capacity_callback() cpufreq notifier
we have to make sure that cap_parsing_failed is not set to true in
parse_cpu_capacity() so that init_cpu_capacity_callback() will bail out
before consuming the CPUFREQ_NOTIFY. The easiest way to achieve this is to
provide the dts file with this property.

Signed-off-by: default avatarDietmar Eggemann <dietmar.eggemann@arm.com>
Change-Id: I2975e457a3817793ac53b0d8b5ff87f7483aa867
Signed-off-by: default avatarChris Redpath <chris.redpath@arm.com>
parent 15bd7f15

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
			#cooling-cells = <2>; /* min followed by max */

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			dynamic-power-coefficient = <311>;

			capacity-dmips-mhz = <1024>;

		};



		cpu1: cpu@1 {
@@ -103,6 +104,7 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu2: cpu@2 {
@@ -113,6 +115,7 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu3: cpu@3 {
@@ -123,6 +126,7 @@ 
			next-level-cache = <&CLUSTER0_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu4: cpu@100 {
@@ -133,6 +137,7 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu5: cpu@101 {
@@ -143,6 +148,7 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu6: cpu@102 {
@@ -153,6 +159,7 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		cpu7: cpu@103 {
@@ -163,6 +170,7 @@ 
			next-level-cache = <&CLUSTER1_L2>;

			operating-points-v2 = <&cpu_opp_table>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;

			capacity-dmips-mhz = <1024>;

		};



		CLUSTER0_L2: l2-cache0 {