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Commit 4ae8bdf7 authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

coresight: tmc: Clear CacheCtrlBit2 and CacheCtrlBit3 



TMC ETR should be set to non-cachable and bufferable.
CacheCtrlBit2 and CacheCtrlBit3 should be set 0.

Change-Id: I4d45fa1dccb4c4a33b725e5ecac80679902451a7
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 5003c472

drivers/hwtracing/coresight/coresight-tmc-etr.c

+2 −1
Original line number Diff line number Diff line
@@ -447,7 +447,8 @@ void tmc_etr_enable_hw(struct tmc_drvdata *drvdata) 
	}



	axictl = (axictl &

		  ~(TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1)) |

		  ~(TMC_AXICTL_CACHE_CTL_B0 | TMC_AXICTL_CACHE_CTL_B1 |

		  TMC_AXICTL_CACHE_CTL_B2 | TMC_AXICTL_CACHE_CTL_B3)) |

		  TMC_AXICTL_CACHE_CTL_B0;

	writel_relaxed(axictl, drvdata->base + TMC_AXICTL);

	tmc_write_dba(drvdata, drvdata->paddr);

drivers/hwtracing/coresight/coresight-tmc.h

+2 −0
Original line number Diff line number Diff line
@@ -86,6 +86,8 @@ 
#define TMC_AXICTL_PROT_CTL_B1	BIT(1)

#define TMC_AXICTL_CACHE_CTL_B0	BIT(2)

#define TMC_AXICTL_CACHE_CTL_B1	BIT(3)

#define TMC_AXICTL_CACHE_CTL_B2	BIT(4)

#define TMC_AXICTL_CACHE_CTL_B3	BIT(5)

#define TMC_AXICTL_SCT_GAT_MODE	BIT(7)

#define TMC_AXICTL_WR_BURST_16	0xF00

/* Write-back Read and Write-allocate */