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Commit 4a652719 authored Jul 23, 2018 by Saranya Chidura

ARM: dts: msm: enable ETR SG as default and DCC with LL1 on qcs405



QDSS ETR is enabled as scatter-gather mode and DCC with linked
list 1 as default in QCS405.

Change-Id: I44b8089c39f6f16aab88b5a29bfb5728c22ca3e1
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>

parent 71c317cf

arch/arm64/boot/dts/qcom/qcs405-coresight.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -71,6 +71,7 @@

		arm,buffer-size = <0x400000>;
		qcom,force-reg-dump;
		arm,sg-enable;

		coresight-name = "coresight-tmc-etr";
		coresight-ctis = <&cti0 &cti0>;

arch/arm64/boot/dts/qcom/qcs405.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -404,6 +404,7 @@

		reg-names = "dcc-base", "dcc-ram-base";
		dcc-ram-offset = <0x400>;
		qcom,curr-link-list = <1>;
		};

		rpm_bus: qcom,rpm-smd {