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Commit 4a230fa6 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvd0/disp: calculate U script id in supervisor interrupt 



This is like we do on nv50:nvd9 already.  There's been no problems seen
yet with using this *seemingly* scratch register to store the value, but
we won't be able to do this anymore once nv50's code is merged.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 8e9e3d2d

drivers/gpu/drm/nouveau/core/engine/disp/nv50.c

+1 −0
Original line number Diff line number Diff line
@@ -656,6 +656,7 @@ nv50_disp_base_ofuncs = { 
static struct nouveau_omthds

nv50_disp_base_omthds[] = {

	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },

	{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },

	{},

drivers/gpu/drm/nouveau/core/engine/disp/nv50.h

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ struct nv50_disp_priv { 
		int (*dp_drvctl)(struct nv50_disp_priv *, int sor, int link,

				 int lane, u16 type, u16 mask, u32 data,

				 struct dcb_output *);

		u32 lvdsconf;

	} sor;

};

drivers/gpu/drm/nouveau/core/engine/disp/nv84.c

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ struct nouveau_omthds 
nv84_disp_base_omthds[] = {

	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },

	{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },

	{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_PWR)         , nv50_dac_mthd },

	{ DAC_MTHD(NV50_DISP_DAC_LOAD)        , nv50_dac_mthd },

	{},

drivers/gpu/drm/nouveau/core/engine/disp/nv94.c

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ static struct nouveau_omthds 
nv94_disp_base_omthds[] = {

	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },

	{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },

	{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_TRAIN)    , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL)   , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd },

drivers/gpu/drm/nouveau/core/engine/disp/nva3.c

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ nva3_disp_base_omthds[] = { 
	{ SOR_MTHD(NV50_DISP_SOR_PWR)         , nv50_sor_mthd },

	{ SOR_MTHD(NVA3_DISP_SOR_HDA_ELD)     , nv50_sor_mthd },

	{ SOR_MTHD(NV84_DISP_SOR_HDMI_PWR)    , nv50_sor_mthd },

	{ SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_TRAIN)    , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_LNKCTL)   , nv50_sor_mthd },

	{ SOR_MTHD(NV94_DISP_SOR_DP_DRVCTL(0)), nv50_sor_mthd },