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Commit 49c82f2b authored by Simon Xue's avatar Simon Xue Committed by Heiko Stuebner
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arm64: dts: rockchip: add rk3328 iommu nodes 



Add H265e/VEPU/VPU/VDEC/VOP iommu nodes

Signed-off-by: default avatarSimon Xue <xxm@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 6f2dea1f

arch/arm64/boot/dts/rockchip/rk3328.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -520,6 +520,51 @@ 
		status = "disabled";

	};



	h265e_mmu: iommu@ff330200 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff330200 0 0x100>;

		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "h265e_mmu";

		#iommu-cells = <0>;

		status = "disabled";

	};



	vepu_mmu: iommu@ff340800 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff340800 0x0 0x40>;

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vepu_mmu";

		#iommu-cells = <0>;

		status = "disabled";

	};



	vpu_mmu: iommu@ff350800 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff350800 0x0 0x40>;

		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "vpu_mmu";

		#iommu-cells = <0>;

		status = "disabled";

	};



	rkvdec_mmu: iommu@ff360480 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;

		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "rkvdec_mmu";

		#iommu-cells = <0>;

		status = "disabled";

	};



	vop_mmu: iommu@ff373f00 {

		compatible = "rockchip,iommu";

		reg = <0x0 0xff373f00 0x0 0x100>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;

		interrupt-names = "vop_mmu";

		#iommu-cells = <0>;

		status = "disabled";

	};



	cru: clock-controller@ff440000 {

		compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";

		reg = <0x0 0xff440000 0x0 0x1000>;