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Commit 495db273 authored by Giuseppe Cavallaro's avatar Giuseppe Cavallaro Committed by David S. Miller
Browse files

stmmac: share reset function between dwmac100 and dwmac1000 



This patch is to share the same reset procedure between dwmac100 and
dwmac1000 chips.
This will also help on enhancing the driver and support new chips.

Signed-off-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fcb3f55f

drivers/net/ethernet/stmicro/stmmac/common.h

+2 −1
Original line number Diff line number Diff line
@@ -376,7 +376,8 @@ extern const struct stmmac_desc_ops ndesc_ops; 
/* Specific DMA helpers */

struct stmmac_dma_ops {

	/* DMA core initialization */

	int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,

	int (*reset)(void __iomem *ioaddr);

	void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,

		     int burst_len, u32 dma_tx, u32 dma_rx, int atds);

	/* Dump DMA registers */

	void (*dump_regs) (void __iomem *ioaddr);

drivers/net/ethernet/stmicro/stmmac/dwmac100.h

+0 −1
Original line number Diff line number Diff line
@@ -95,7 +95,6 @@ 
#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */

#define DMA_BUS_MODE_DSL_SHIFT	2	/*   (in DWORDS)      */

#define DMA_BUS_MODE_BAR_BUS	0x00000002	/* Bar-Bus Arbitration */

#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */

#define DMA_BUS_MODE_DEFAULT	0x00000000



/* DMA Control register defines */

drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

+0 −1
Original line number Diff line number Diff line
@@ -221,7 +221,6 @@ enum inter_frame_gap { 


/*--- DMA BLOCK defines ---*/

/* DMA Bus Mode register defines */

#define DMA_BUS_MODE_SFT_RESET	0x00000001	/* Software Reset */

#define DMA_BUS_MODE_DA		0x00000002	/* Arbitration scheme */

#define DMA_BUS_MODE_DSL_MASK	0x0000007c	/* Descriptor Skip Length */

#define DMA_BUS_MODE_DSL_SHIFT	2		/*   (in DWORDS)      */

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+4 −18
Original line number Diff line number Diff line
@@ -30,23 +30,10 @@ 
#include "dwmac1000.h"

#include "dwmac_dma.h"



static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,

static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,

			       int burst_len, u32 dma_tx, u32 dma_rx, int atds)

{

	u32 value = readl(ioaddr + DMA_BUS_MODE);

	int limit;



	/* DMA SW reset */

	value |= DMA_BUS_MODE_SFT_RESET;

	writel(value, ioaddr + DMA_BUS_MODE);

	limit = 10;

	while (limit--) {

		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))

			break;

		mdelay(10);

	}

	if (limit < 0)

		return -EBUSY;

	u32 value;



	/*

	 * Set the DMA PBL (Programmable Burst Length) mode
@@ -102,8 +89,6 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, 
	 */

	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);

	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);



	return 0;

}



static u32 dwmac1000_configure_fc(u32 csr6, int rxfifosz)
@@ -205,6 +190,7 @@ static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt) 
}



const struct stmmac_dma_ops dwmac1000_dma_ops = {

	.reset = dwmac_dma_reset,

	.init = dwmac1000_dma_init,

	.dump_regs = dwmac1000_dump_dma_regs,

	.dma_mode = dwmac1000_dma_operation_mode,

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+3 −19
Original line number Diff line number Diff line
@@ -32,24 +32,9 @@ 
#include "dwmac100.h"

#include "dwmac_dma.h"



static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,

static void dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,

			      int burst_len, u32 dma_tx, u32 dma_rx, int atds)

{

	u32 value = readl(ioaddr + DMA_BUS_MODE);

	int limit;



	/* DMA SW reset */

	value |= DMA_BUS_MODE_SFT_RESET;

	writel(value, ioaddr + DMA_BUS_MODE);

	limit = 10;

	while (limit--) {

		if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))

			break;

		mdelay(10);

	}

	if (limit < 0)

		return -EBUSY;



	/* Enable Application Access by writing to DMA CSR0 */

	writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT),

	       ioaddr + DMA_BUS_MODE);
@@ -62,8 +47,6 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, 
	 */

	writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);

	writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);



	return 0;

}



/* Store and Forward capability is not used at all.
@@ -131,6 +114,7 @@ static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 
}



const struct stmmac_dma_ops dwmac100_dma_ops = {

	.reset = dwmac_dma_reset,

	.init = dwmac100_dma_init,

	.dump_regs = dwmac100_dump_dma_regs,

	.dma_mode = dwmac100_dma_operation_mode,