Commit 48e5d68d authored May 03, 2016 by Imre Deak

drm/i915/bdw: Add missing delay during L3 SQC credit programming



BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.

CC: stable@vger.kernel.org
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-2-git-send-email-imre.deak@intel.com

parent 9a41e17d

drivers/gpu/drm/i915/intel_pm.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -6738,6 +6738,12 @@ static void broadwell_init_clock_gating(struct drm_device *dev)
		misccpctl = I915_READ(GEN7_MISCCPCTL);
		I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
		I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
		/*
		* Wait at least 100 clocks before re-enabling clock gating. See
		* the definition of L3SQCREG1 in BSpec.
		*/
		POSTING_READ(GEN8_L3SQCREG1);
		udelay(1);
		I915_WRITE(GEN7_MISCCPCTL, misccpctl);

		/*