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Commit 48d7b759 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: add vce state tables initialize for ppt v1. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 791a57db

drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c

+58 −0
Original line number Diff line number Diff line
@@ -1164,6 +1164,54 @@ static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, 
	return result;

}



static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)

{

	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);

	const ATOM_Tonga_VCE_State_Table *vce_state_table =

				(ATOM_Tonga_VCE_State_Table *)(((unsigned long)pp_table) + le16_to_cpu(pp_table->usVCEStateTableOffset));



	if (vce_state_table == NULL)

		return 0;



	return vce_state_table->ucNumEntries;

}





static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,

		struct pp_vce_state *vce_state, void **clock_info, uint32_t *flag)

{

	const ATOM_Tonga_VCE_State_Record *vce_state_record;

	const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr);

	const ATOM_Tonga_VCE_State_Table *vce_state_table = (ATOM_Tonga_VCE_State_Table *)(((unsigned long)pptable)

							  + le16_to_cpu(pptable->usVCEStateTableOffset));

	const ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table = (ATOM_Tonga_SCLK_Dependency_Table *)(((unsigned long)pptable)

							  + le16_to_cpu(pptable->usSclkDependencyTableOffset));

	const ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = (ATOM_Tonga_MCLK_Dependency_Table *)(((unsigned long)pptable)

							  + le16_to_cpu(pptable->usMclkDependencyTableOffset));

	const ATOM_Tonga_MM_Dependency_Table *mm_dep_table = (ATOM_Tonga_MM_Dependency_Table *)(((unsigned long)pptable)

							  + le16_to_cpu(pptable->usMMDependencyTableOffset));



	PP_ASSERT_WITH_CODE((i < vce_state_table->ucNumEntries),

			 "Requested state entry ID is out of range!",

			 return -EINVAL);



	vce_state_record = (ATOM_Tonga_VCE_State_Record *)((char *)&vce_state_table->entries[1]

				+ (sizeof(ATOM_Tonga_VCE_State_Record) * i));



	*flag = vce_state_record->ucFlag;



	vce_state->evclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk;

	vce_state->ecclk = mm_dep_table->entries[vce_state_record->ucVCEClockIndex].ulEClk;

	vce_state->sclk = sclk_dep_table->entries[vce_state_record->ucSCLKIndex].ulSclk;



	if (vce_state_record->ucMCLKIndex >= mclk_dep_table->ucNumEntries)

		vce_state->mclk = mclk_dep_table->entries[mclk_dep_table->ucNumEntries - 1].ulMclk;

	else

		vce_state->mclk = mclk_dep_table->entries[vce_state_record->ucMCLKIndex].ulMclk;



	return 0;

}



/**

* Create a Power State out of an entry in the PowerPlay table.

* This function is called by the hardware back-end.
@@ -1181,6 +1229,8 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, 
	const ATOM_Tonga_State_Array * state_arrays;

	const ATOM_Tonga_State *state_entry;

	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);

	int i, j;

	uint32_t flags = 0;



	PP_ASSERT_WITH_CODE((NULL != pp_table), "Missing PowerPlay Table!", return -1;);

	power_state->classification.bios_index = entry_index;
@@ -1210,5 +1260,13 @@ int tonga_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, 
			PP_StateClassificationFlag_Boot))

		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));



	hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);



	if ((i != 0) && (i <= PP_MAX_VCE_LEVELS)) {

		for (j = 0; j < i; j++)

			ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);

	}



	return result;

}

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+17 −5
Original line number Diff line number Diff line
@@ -31,16 +31,13 @@ 
#include "hwmgr_ppt.h"

#include "ppatomctrl.h"

#include "hwmgr_ppt.h"

#include "power_state.h"



struct pp_instance;

struct pp_hwmgr;

struct pp_hw_power_state;

struct pp_power_state;

struct pp_vce_state;

struct phm_fan_speed_info;

struct pp_atomctrl_voltage_table;





extern int amdgpu_powercontainment;

extern int amdgpu_sclk_deep_sleep_en;
@@ -52,7 +49,6 @@ enum DISPLAY_GAP { 
};

typedef enum DISPLAY_GAP DISPLAY_GAP;





struct vi_dpm_level {

	bool enabled;

	uint32_t value;
@@ -573,6 +569,18 @@ struct phm_microcode_version_info { 
	uint32_t NB;

};



#define PP_MAX_VCE_LEVELS 6



enum PP_VCE_LEVEL {

	PP_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */

	PP_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */

	PP_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */

	PP_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */

	PP_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */

	PP_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */

};





/**

 * The main hardware manager structure.

 */
@@ -586,6 +594,10 @@ struct pp_hwmgr { 
	uint32_t soft_pp_table_size;

	void *hardcode_pp_table;

	bool need_pp_table_upload;



	struct pp_vce_state vce_states[PP_MAX_VCE_LEVELS];

	uint32_t num_vce_state_tables;



	enum amd_dpm_forced_level dpm_level;

	bool block_hw_access;

	struct phm_gfx_arbiter gfx_arbiter;