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Commit 48d64738 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ais: enable ife line mode"

parents 595749e8 27824210
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+1 −1
Original line number Diff line number Diff line
@@ -1325,7 +1325,7 @@ static int cam_ife_mgr_acquire_cid_res(
	 * Using reserved field to receive ifeId from UMD and Acquiring
	 * corresponding IFE resource only if available
	 */
	ife_id = out_port->reserved;
	ife_id = out_port->reserved & 0xFF;

	if ((ife_id >= CAM_IFE_CSID_HW_NUM_MAX) ||
		(!ife_hw_mgr->csid_devices[ife_id])) {
+24 −22
Original line number Diff line number Diff line
@@ -924,6 +924,17 @@ static int cam_vfe_bus_acquire_wm(

	if (rsrc_data->index < 3) {
		/* Write master 0-2 refers to RDI 0/ RDI 1/RDI 2 */
		if ((out_port_info->reserved >> 8) & 0x01) {
			/* frame based mode as default */
			rsrc_data->width =
			CAM_VFE_RDI_BUS_DEFAULT_WIDTH;
			rsrc_data->height = 0;
			rsrc_data->stride =
			CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
			rsrc_data->en_cfg = 0x3;
		} else {
			rsrc_data->en_cfg = 0x1;
		}
		switch (rsrc_data->format) {
		case CAM_FORMAT_MIPI_RAW_6:
		case CAM_FORMAT_MIPI_RAW_8:
@@ -933,31 +944,24 @@ static int cam_vfe_bus_acquire_wm(
		case CAM_FORMAT_MIPI_RAW_16:
		case CAM_FORMAT_MIPI_RAW_20:
		case CAM_FORMAT_PLAIN128:
			rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH;
			rsrc_data->height = 0;
			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
			rsrc_data->pack_fmt = 0x0;
			rsrc_data->en_cfg = 0x3;
			break;
		case CAM_FORMAT_PLAIN8:
			rsrc_data->en_cfg = 0x1;
			rsrc_data->pack_fmt = 0x1;
			rsrc_data->width = rsrc_data->width * 2;
			rsrc_data->stride = rsrc_data->width;
			break;
		case CAM_FORMAT_PLAIN16_10:
			rsrc_data->pack_fmt = 0x2;
			break;
		case CAM_FORMAT_PLAIN16_12:
			rsrc_data->pack_fmt = 0x3;
			break;
		case CAM_FORMAT_PLAIN16_14:
			rsrc_data->pack_fmt = 0x4;
			break;
		case CAM_FORMAT_PLAIN16_16:
		case CAM_FORMAT_PLAIN32_20:
			rsrc_data->width = CAM_VFE_RDI_BUS_DEFAULT_WIDTH;
			rsrc_data->height = 0;
			rsrc_data->stride = CAM_VFE_RDI_BUS_DEFAULT_STRIDE;
			rsrc_data->pack_fmt = 0x0;
			rsrc_data->en_cfg = 0x3;
			rsrc_data->pack_fmt = 0x5;
			break;
		case CAM_FORMAT_PLAIN64:
			rsrc_data->en_cfg = 0x1;
			rsrc_data->pack_fmt = 0xA;
			break;
		default:
@@ -2886,14 +2890,12 @@ static int cam_vfe_bus_update_wm(void *priv, void *cmd_args,
				io_cfg->planes[i].plane_stride,
				val);

		if (wm_data->index >= 3) {
		CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
			wm_data->hw_regs->stride,
			io_cfg->planes[i].plane_stride);
		wm_data->stride = val;
		CAM_DBG(CAM_ISP, "WM %d image stride 0x%x",
			wm_data->index, reg_val_pair[j-1]);
		}

		if (wm_data->en_ubwc) {
			if (!wm_data->hw_regs->ubwc_regs) {