Loading arch/arm64/boot/dts/qcom/qcs405.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -319,11 +319,15 @@ status = "disabled"; }; blsp1_uart2: serial@78b0000 { blsp1_uart1: serial@78b0000 { compatible = "qcom,msm-uartdm", "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "okay"; }; dcc: dcc_v2@b2000 { Loading Loading
arch/arm64/boot/dts/qcom/qcs405.dtsi +5 −1 Original line number Diff line number Diff line Loading @@ -319,11 +319,15 @@ status = "disabled"; }; blsp1_uart2: serial@78b0000 { blsp1_uart1: serial@78b0000 { compatible = "qcom,msm-uartdm", "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>; interrupts = <0 108 0>; clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "okay"; }; dcc: dcc_v2@b2000 { Loading