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Commit 484205df authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

A little bigger than usual since it's two weeks worth.  Highlights:
- Add support for new smc firmware on some new hainan variants
- add support for SI chips that require special mc firmware
- remove workarounds for issues fixed by new mc firmware
- fix a regression in cursor handling
- various VCE fixes
- fix for UVD clockgating

* 'drm-fixes-4.10' of git://people.freedesktop.org/~agd5f/linux:
  drm/amdgpu: add support for new hainan variants
  drm/radeon: add support for new hainan variants
  drm/amdgpu: change clock gating mode for uvd_v4.
  drm/amdgpu: fix program vce instance logic error.
  drm/amdgpu: fix bug set incorrect value to vce register
  Revert "drm/amdgpu: Only update the CUR_SIZE register when necessary"
  drm/amd/powerplay: refine vce dpm update code on Cz.
  drm/amdgpu: fix vm_fault_stop on gfx6
  drm/amd/powerplay: fix vce cg logic error on CZ/St.
  drm/radeon: drop the mclk quirk for hainan
  drm/radeon: drop oland quirks
  drm/amdgpu: drop the mclk quirk for hainan
  drm/amdgpu: drop oland quirks
  drm/amdgpu/si: load special ucode for certain MC configs
  drm/radeon/si: load special ucode for certain MC configs
parents b3103485 17324b6a

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2512,6 +2512,8 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2537,7 +2539,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				      int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2578,7 +2579,9 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v10_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2587,16 +2590,10 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v10_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v10_0_show_cursor(crtc);
@@ -2620,7 +2617,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v10_0_lock_cursor(crtc, true);
@@ -2628,10 +2624,6 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					     amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v10_0_show_cursor(crtc);



		dce_v10_0_lock_cursor(crtc, false);

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2532,6 +2532,8 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2557,7 +2559,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				      int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2598,7 +2599,9 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v11_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2607,16 +2610,10 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v11_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v11_0_show_cursor(crtc);
@@ -2640,7 +2637,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v11_0_lock_cursor(crtc, true);
@@ -2648,10 +2644,6 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					     amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v11_0_show_cursor(crtc);



		dce_v11_0_lock_cursor(crtc, false);

drivers/gpu/drm/amd/amdgpu/dce_v6_0.c

+9 −15
Original line number Diff line number Diff line
@@ -1859,6 +1859,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 
	struct amdgpu_device *adev = crtc->dev->dev_private;

	int xorigin = 0, yorigin = 0;



	int w = amdgpu_crtc->cursor_width;



	amdgpu_crtc->cursor_x = x;

	amdgpu_crtc->cursor_y = y;
@@ -1878,6 +1880,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -1903,7 +1907,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				     int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -1944,7 +1947,9 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v6_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -1953,16 +1958,10 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v6_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v6_0_show_cursor(crtc);
@@ -1986,7 +1985,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v6_0_lock_cursor(crtc, true);
@@ -1994,10 +1992,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					    amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v6_0_show_cursor(crtc);

		dce_v6_0_lock_cursor(crtc, false);

	}

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+7 −15
Original line number Diff line number Diff line
@@ -2363,6 +2363,8 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 


	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));



	return 0;

}
@@ -2388,7 +2390,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 
				     int32_t hot_y)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;

	struct drm_gem_object *obj;

	struct amdgpu_bo *aobj;

	int ret;
@@ -2429,7 +2430,9 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 


	dce_v8_0_lock_cursor(crtc, true);



	if (hot_x != amdgpu_crtc->cursor_hot_x ||

	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height ||

	    hot_x != amdgpu_crtc->cursor_hot_x ||

	    hot_y != amdgpu_crtc->cursor_hot_y) {

		int x, y;
@@ -2438,16 +2441,10 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 


		dce_v8_0_cursor_move_locked(crtc, x, y);



		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	if (width != amdgpu_crtc->cursor_width ||

	    height != amdgpu_crtc->cursor_height) {

		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (width - 1) << 16 | (height - 1));

		amdgpu_crtc->cursor_width = width;

		amdgpu_crtc->cursor_height = height;

		amdgpu_crtc->cursor_hot_x = hot_x;

		amdgpu_crtc->cursor_hot_y = hot_y;

	}



	dce_v8_0_show_cursor(crtc);
@@ -2471,7 +2468,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 
static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)

{

	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);

	struct amdgpu_device *adev = crtc->dev->dev_private;



	if (amdgpu_crtc->cursor_bo) {

		dce_v8_0_lock_cursor(crtc, true);
@@ -2479,10 +2475,6 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 
		dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,

					    amdgpu_crtc->cursor_y);



		WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

		       (amdgpu_crtc->cursor_width - 1) << 16 |

		       (amdgpu_crtc->cursor_height - 1));



		dce_v8_0_show_cursor(crtc);



		dce_v8_0_lock_cursor(crtc, false);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+19 −15
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ MODULE_FIRMWARE("radeon/tahiti_mc.bin"); 
MODULE_FIRMWARE("radeon/pitcairn_mc.bin");

MODULE_FIRMWARE("radeon/verde_mc.bin");

MODULE_FIRMWARE("radeon/oland_mc.bin");

MODULE_FIRMWARE("radeon/si58_mc.bin");



#define MC_SEQ_MISC0__MT__MASK   0xf0000000

#define MC_SEQ_MISC0__MT__GDDR1  0x10000000
@@ -113,6 +114,7 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 
	const char *chip_name;

	char fw_name[30];

	int err;

	bool is_58_fw = false;



	DRM_DEBUG("\n");
@@ -135,6 +137,13 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 
	default: BUG();

	}



	/* this memory configuration requires special firmware */

	if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)

		is_58_fw = true;



	if (is_58_fw)

		snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin");

	else

		snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);

	err = request_firmware(&adev->mc.fw, fw_name, adev->dev);

	if (err)
@@ -463,19 +472,11 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 
	WREG32(mmVM_CONTEXT1_CNTL,

	       VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |

	       (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |

	       ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT) |

	       VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |

	       VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |

	       VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |

	       VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |

	       VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK |

	       VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |

	       VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);

	       ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));

	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)

		gmc_v6_0_set_fault_enable_default(adev, false);

	else

		gmc_v6_0_set_fault_enable_default(adev, true);



	gmc_v6_0_gart_flush_gpu_tlb(adev, 0);

	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -754,7 +755,10 @@ static int gmc_v6_0_late_init(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)

		return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);

	else

		return 0;

}



static int gmc_v6_0_sw_init(void *handle)