Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 46d4bca0 authored by Florian Fainelli's avatar Florian Fainelli
Browse files

ARM: BCM63XX: add BCM63138 minimal Device Tree 



Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:

- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)

Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.

Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parent b51312be

arch/arm/boot/dts/bcm63138.dtsi

0 → 100644
+134 −0
Original line number Original line Diff line number Diff line 
/*

 * Broadcom BCM63138 DSL SoCs Device Tree

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>



#include "skeleton.dtsi"



/ {

	compatible = "brcm,bcm63138";

	model = "Broadcom BCM63138 DSL SoC";

	interrupt-parent = <&gic>;



	aliases {

		uart0 = &serial0;

		uart1 = &serial1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <0>;

		};



		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			next-level-cache = <&L2>;

			reg = <1>;

		};

	};



	clocks {

		#address-cells = <1>;

		#size-cells = <0>;



		arm_timer_clk: arm_timer_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <500000000>;

		};



		periph_clk: periph_clk {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			clock-frequency = <50000000>;

			clock-output-names = "periph";

		};

	};



	/* ARM bus */

	axi@80000000 {

		compatible = "simple-bus";

		ranges = <0 0x80000000 0x784000>;

		#address-cells = <1>;

		#size-cells = <1>;



		L2: cache-controller@1d000 {

			compatible = "arm,pl310-cache";

			reg = <0x1d000 0x1000>;

			cache-unified;

			cache-level = <2>;

			cache-sets = <16>;

			cache-size = <0x80000>;

			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;

		};



		scu: scu@1e000 {

			compatible = "arm,cortex-a9-scu";

			reg = <0x1e000 0x100>;

		};



		gic: interrupt-controller@1e100 {

			compatible = "arm,cortex-a9-gic";

			reg = <0x1f000 0x1000

				0x1e100 0x100>;

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

		};



		global_timer: timer@1e200 {

			compatible = "arm,cortex-a9-global-timer";

			reg = <0x1e200 0x20>;

			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&arm_timer_clk>;

		};



		local_timer: local-timer@1e600 {

			compatible = "arm,cortex-a9-twd-timer";

			reg = <0x1e600 0x20>;

			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&arm_timer_clk>;

		};



		twd_watchdog: watchdog@1e620 {

			compatible = "arm,cortex-a9-twd-wdt";

			reg = <0x1e620 0x20>;

			interupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	/* Legacy UBUS base */

	ubus@fffe8000 {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0xfffe8000 0x8100>;



		serial0: serial@600 {

			compatible = "brcm,bcm6345-uart";

			reg = <0x600 0x1b>;

			interrupts = <GIC_SPI 32 0>;

			clocks = <&periph_clk>;

			clock-names = "periph";

			status = "disabled";

		};



		serial1: serial@620 {

			compatible = "brcm,bcm6345-uart";

			reg = <0x620 0x1b>;

			interrupts = <GIC_SPI 33 0>;

			clocks = <&periph_clk>;

			clock-names = "periph";

			status = "disabled";

		};

	};

};