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Commit 460684e1 authored by Xu Yang's avatar Xu Yang Committed by Gerrit - the friendly Code Review server
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disp: msm: sde: Update gamut non-uniform support 



New version of the gamut block has been introduced with changes to
the scale/offset programming. Change updates the minor version for
the feature.

Change-Id: I62597a9d229e13e10e0ac0f1183b2db2b0b2a575
Signed-off-by: default avatarXu Yang <yangxu@codeaurora.org>
parent 4abb683f

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+12 −0
Original line number Diff line number Diff line
@@ -171,6 +171,18 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) 
					c->ops.setup_gamut =

					    sde_setup_dspp_3d_gamutv41;

				}

			} else if (c->cap->sblk->gamut.version ==

					SDE_COLOR_PROCESS_VER(0x4, 2)) {

				ret = reg_dmav1_init_dspp_op_v4(

					SDE_DSPP_GAMUT, c->idx);

				c->ops.setup_gamut = NULL;

				if (!ret) {

					c->ops.setup_gamut =

					    reg_dmav1_setup_dspp_3d_gamutv42;

				} else {

					c->ops.setup_gamut =

					    sde_setup_dspp_3d_gamutv41;

				}

			}

			break;

		case SDE_DSPP_GC:

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.c

+40 −0
Original line number Diff line number Diff line
@@ -615,6 +615,46 @@ void reg_dmav1_setup_dspp_3d_gamutv41(struct sde_hw_dspp *ctx, void *cfg) 
		GAMUT_SCALE_OFF_LEN);

}



void reg_dmav1_setup_dspp_3d_gamutv42(struct sde_hw_dspp *ctx, void *cfg)

{

	struct sde_hw_cp_cfg *hw_cfg = cfg;

	struct drm_msm_3d_gamut *payload = NULL;

	uint32_t i, j, tmp;

	uint32_t scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];

	int rc;



	rc = reg_dma_dspp_check(ctx, cfg, GAMUT);

	if (rc)

		return;

	if (hw_cfg->payload && hw_cfg->len != sizeof(struct drm_msm_3d_gamut)) {

		DRM_ERROR("invalid payload len actual %d expected %zd",

				hw_cfg->len, sizeof(struct drm_msm_3d_gamut));

		return;

	}



	payload = hw_cfg->payload;

	if (payload && (payload->flags & GAMUT_3D_MAP_EN)) {

		for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {

			for (j = 0; j < GAMUT_3D_SCALE_OFF_SZ; j++) {

				scale_off[i][j] = payload->scale_off[i][j];

				tmp = payload->scale_off[i][j] & 0x1ffff000;

				payload->scale_off[i][j] &= 0xfff;

				tmp = tmp << 3;

				payload->scale_off[i][j] =

					tmp | payload->scale_off[i][j];

			}

		}

	}

	reg_dmav1_setup_dspp_3d_gamutv4_common(ctx, cfg, GAMUT_SCALE_OFF_LEN,

		GAMUT_SCALE_OFF_LEN);

	if (payload && (payload->flags & GAMUT_3D_MAP_EN)) {

		for (i = 0; i < GAMUT_3D_SCALE_OFF_TBL_NUM; i++) {

			for (j = 0; j < GAMUT_3D_SCALE_OFF_SZ; j++)

				payload->scale_off[i][j] = scale_off[i][j];

		}

	}

}



void reg_dmav1_setup_dspp_gcv18(struct sde_hw_dspp *ctx, void *cfg)

{

	struct drm_msm_pgc_lut *lut_cfg;

drivers/gpu/drm/msm/sde/sde_hw_reg_dma_v1_color_proc.h

+7 −0
Original line number Diff line number Diff line
@@ -46,6 +46,13 @@ void reg_dmav1_setup_dspp_3d_gamutv4(struct sde_hw_dspp *ctx, void *cfg); 
 */

void reg_dmav1_setup_dspp_3d_gamutv41(struct sde_hw_dspp *ctx, void *cfg);



/**

 * reg_dmav1_setup_3d_gamutv42() - gamut v4_2 implementation using reg dma v1.

 * @ctx: dspp ctx info

 * @cfg: pointer to struct sde_hw_cp_cfg

 */

void reg_dmav1_setup_dspp_3d_gamutv42(struct sde_hw_dspp *ctx, void *cfg);



/**

 * reg_dmav1_setup_dspp_gcv18() - gc v18 implementation using reg dma v1.

 * @ctx: dspp ctx info