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Commit 45c8dbed authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.14.29 into android-4.14 



Changes in 4.14.29
	x86/cpufeatures: Add Intel Total Memory Encryption cpufeature
	x86/cpufeatures: Add Intel PCONFIG cpufeature
	selftests/x86/entry_from_vm86: Exit with 1 if we fail
	selftests/x86: Add tests for User-Mode Instruction Prevention
	selftests/x86: Add tests for the STR and SLDT instructions
	selftests/x86/entry_from_vm86: Add test cases for POPF
	x86/vm86/32: Fix POPF emulation
	x86/speculation, objtool: Annotate indirect calls/jumps for objtool on 32-bit kernels
	x86/speculation: Remove Skylake C2 from Speculation Control microcode blacklist
	KVM: x86: Fix device passthrough when SME is active
	x86/mm: Fix vmalloc_fault to use pXd_large
	parisc: Handle case where flush_cache_range is called with no context
	ALSA: pcm: Fix UAF in snd_pcm_oss_get_formats()
	ALSA: hda - Revert power_save option default value
	ALSA: seq: Fix possible UAF in snd_seq_check_queue()
	ALSA: seq: Clear client entry before deleting else at closing
	drm/nouveau/bl: Fix oops on driver unbind
	drm/amdgpu: fix prime teardown order
	drm/radeon: fix prime teardown order
	drm/amdgpu/dce: Don't turn off DP sink when disconnected
	fs: Teach path_connected to handle nfs filesystems with multiple roots.
	KVM: arm/arm64: Reduce verbosity of KVM init log
	kvm: arm/arm64: vgic-v3: Tighten synchronization for guests using v2 on v3
	KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid
	lock_parent() needs to recheck if dentry got __dentry_kill'ed under it
	fs/aio: Add explicit RCU grace period when freeing kioctx
	fs/aio: Use RCU accessors for kioctx_table->table[]
	RDMAVT: Fix synchronization around percpu_ref
	irqchip/gic-v3-its: Ensure nr_ites >= nr_lpis
	btrfs: Fix NULL pointer exception in find_bio_stripe
	btrfs: add missing initialization in btrfs_check_shared
	btrfs: alloc_chunk: fix DUP stripe size handling
	btrfs: Fix use-after-free when cleaning up fs_devs with a single stale device
	btrfs: remove spurious WARN_ON(ref->count < 0) in find_parent_nodes
	btrfs: Fix memory barriers usage with device stats counters
	scsi: qla2xxx: Fix smatch warning in qla25xx_delete_{rsp|req}_que
	scsi: qla2xxx: Fix NULL pointer access for fcport structure
	scsi: qla2xxx: Fix logo flag for qlt_free_session_done()
	scsi: qla2xxx: Fix crashes in qla2x00_probe_one on probe failure
	USB: gadget: udc: Add missing platform_device_put() on error in bdc_pci_probe()
	usb: dwc3: Fix GDBGFIFOSPACE_TYPE values
	Linux 4.14.29

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents e707f486 80960794

Makefile

+1 −1
Original line number Original line Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

# SPDX-License-Identifier: GPL-2.0

VERSION = 4

VERSION = 4

PATCHLEVEL = 14

PATCHLEVEL = 14

SUBLEVEL = 28

SUBLEVEL = 29

EXTRAVERSION =

EXTRAVERSION =

NAME = Petit Gorille

NAME = Petit Gorille

arch/parisc/kernel/cache.c

+32 −9
Original line number Original line Diff line number Diff line
@@ -543,6 +543,7 @@ void flush_cache_mm(struct mm_struct *mm) 
	   rp3440, etc.  So, avoid it if the mm isn't too big.  */

	   rp3440, etc.  So, avoid it if the mm isn't too big.  */

	if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&

	if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&

	    mm_total_size(mm) >= parisc_cache_flush_threshold) {

	    mm_total_size(mm) >= parisc_cache_flush_threshold) {

		if (mm->context)

			flush_tlb_all();

			flush_tlb_all();

		flush_cache_all();

		flush_cache_all();

		return;

		return;
@@ -571,6 +572,8 @@ void flush_cache_mm(struct mm_struct *mm) 
			pfn = pte_pfn(*ptep);

			pfn = pte_pfn(*ptep);

			if (!pfn_valid(pfn))

			if (!pfn_valid(pfn))

				continue;

				continue;

			if (unlikely(mm->context))

				flush_tlb_page(vma, addr);

			__flush_cache_page(vma, addr, PFN_PHYS(pfn));

			__flush_cache_page(vma, addr, PFN_PHYS(pfn));

		}

		}

	}

	}
@@ -579,25 +582,45 @@ void flush_cache_mm(struct mm_struct *mm) 
void flush_cache_range(struct vm_area_struct *vma,

void flush_cache_range(struct vm_area_struct *vma,

		unsigned long start, unsigned long end)

		unsigned long start, unsigned long end)

{

{

	pgd_t *pgd;

	unsigned long addr;



	if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&

	if ((!IS_ENABLED(CONFIG_SMP) || !arch_irqs_disabled()) &&

	    end - start >= parisc_cache_flush_threshold) {

	    end - start >= parisc_cache_flush_threshold) {

		if (vma->vm_mm->context)

			flush_tlb_range(vma, start, end);

			flush_tlb_range(vma, start, end);

		flush_cache_all();

		flush_cache_all();

		return;

		return;

	}

	}





	if (vma->vm_mm->context == mfsp(3)) {

		flush_user_dcache_range_asm(start, end);

		flush_user_dcache_range_asm(start, end);

		if (vma->vm_flags & VM_EXEC)

		if (vma->vm_flags & VM_EXEC)

			flush_user_icache_range_asm(start, end);

			flush_user_icache_range_asm(start, end);

		flush_tlb_range(vma, start, end);

		flush_tlb_range(vma, start, end);

		return;

	}



	pgd = vma->vm_mm->pgd;

	for (addr = vma->vm_start; addr < vma->vm_end; addr += PAGE_SIZE) {

		unsigned long pfn;

		pte_t *ptep = get_ptep(pgd, addr);

		if (!ptep)

			continue;

		pfn = pte_pfn(*ptep);

		if (pfn_valid(pfn)) {

			if (unlikely(vma->vm_mm->context))

				flush_tlb_page(vma, addr);

			__flush_cache_page(vma, addr, PFN_PHYS(pfn));

		}

	}

}

}





void

void

flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)

flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)

{

{

	BUG_ON(!vma->vm_mm->context);



	if (pfn_valid(pfn)) {

	if (pfn_valid(pfn)) {

		if (likely(vma->vm_mm->context))

			flush_tlb_page(vma, vmaddr);

			flush_tlb_page(vma, vmaddr);

		__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));

		__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));

	}

	}

arch/x86/include/asm/cpufeatures.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -314,6 +314,7 @@ 
#define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */

#define X86_FEATURE_VPCLMULQDQ		(16*32+10) /* Carry-Less Multiplication Double Quadword */

#define X86_FEATURE_AVX512_VNNI		(16*32+11) /* Vector Neural Network Instructions */

#define X86_FEATURE_AVX512_VNNI		(16*32+11) /* Vector Neural Network Instructions */

#define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */

#define X86_FEATURE_AVX512_BITALG	(16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */

#define X86_FEATURE_TME			(16*32+13) /* Intel Total Memory Encryption */

#define X86_FEATURE_AVX512_VPOPCNTDQ	(16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_AVX512_VPOPCNTDQ	(16*32+14) /* POPCNT for vectors of DW/QW */

#define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */

#define X86_FEATURE_LA57		(16*32+16) /* 5-level page tables */

#define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */

#define X86_FEATURE_RDPID		(16*32+22) /* RDPID instruction */
@@ -326,6 +327,7 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */

arch/x86/include/asm/nospec-branch.h

+4 −1
Original line number Original line Diff line number Diff line
@@ -183,7 +183,10 @@ 
 * otherwise we'll run out of registers. We don't care about CET

 * otherwise we'll run out of registers. We don't care about CET

 * here, anyway.

 * here, anyway.

 */

 */

# define CALL_NOSPEC ALTERNATIVE("call *%[thunk_target]\n",	\

# define CALL_NOSPEC						\

	ALTERNATIVE(						\

	ANNOTATE_RETPOLINE_SAFE					\

	"call *%[thunk_target]\n",				\

	"       jmp    904f;\n"					\

	"       jmp    904f;\n"					\

	"       .align 16\n"					\

	"       .align 16\n"					\

	"901:	call   903f;\n"					\

	"901:	call   903f;\n"					\

arch/x86/kernel/cpu/intel.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -105,7 +105,7 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) 
/*

/*

 * Early microcode releases for the Spectre v2 mitigation were broken.

 * Early microcode releases for the Spectre v2 mitigation were broken.

 * Information taken from;

 * Information taken from;

 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/01/microcode-update-guidance.pdf

 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf

 * - https://kb.vmware.com/s/article/52345

 * - https://kb.vmware.com/s/article/52345

 * - Microcode revisions observed in the wild

 * - Microcode revisions observed in the wild

 * - Release note from 20180108 microcode release

 * - Release note from 20180108 microcode release
@@ -123,7 +123,6 @@ static const struct sku_microcode spectre_bad_microcodes[] = { 
	{ INTEL_FAM6_KABYLAKE_MOBILE,	0x09,	0x80 },

	{ INTEL_FAM6_KABYLAKE_MOBILE,	0x09,	0x80 },

	{ INTEL_FAM6_SKYLAKE_X,		0x03,	0x0100013e },

	{ INTEL_FAM6_SKYLAKE_X,		0x03,	0x0100013e },

	{ INTEL_FAM6_SKYLAKE_X,		0x04,	0x0200003c },

	{ INTEL_FAM6_SKYLAKE_X,		0x04,	0x0200003c },

	{ INTEL_FAM6_SKYLAKE_DESKTOP,	0x03,	0xc2 },

	{ INTEL_FAM6_BROADWELL_CORE,	0x04,	0x28 },

	{ INTEL_FAM6_BROADWELL_CORE,	0x04,	0x28 },

	{ INTEL_FAM6_BROADWELL_GT3E,	0x01,	0x1b },

	{ INTEL_FAM6_BROADWELL_GT3E,	0x01,	0x1b },

	{ INTEL_FAM6_BROADWELL_XEON_D,	0x02,	0x14 },

	{ INTEL_FAM6_BROADWELL_XEON_D,	0x02,	0x14 },