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Commit 4576e0ec authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.14.26 into android-4.14 



Changes in 4.14.26
	bpf: fix mlock precharge on arraymaps
	bpf: fix memory leak in lpm_trie map_free callback function
	bpf: fix rcu lockdep warning for lpm_trie map_free callback
	bpf, x64: implement retpoline for tail call
	bpf, arm64: fix out of bounds access in tail call
	bpf: add schedule points in percpu arrays management
	bpf: allow xadd only on aligned memory
	bpf, ppc64: fix out of bounds access in tail call
	KVM: x86: fix backward migration with async_PF
	Linux 4.14.26

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
parents 732ccfad 96427a51

Documentation/virtual/kvm/cpuid.txt

+4 −0
Original line number Diff line number Diff line
@@ -54,6 +54,10 @@ KVM_FEATURE_PV_UNHALT || 7 || guest checks this feature bit 
                                   ||       || before enabling paravirtualized

                                   ||       || spinlock support.

------------------------------------------------------------------------------

KVM_FEATURE_ASYNC_PF_VMEXIT        ||    10 || paravirtualized async PF VM exit

                                   ||       || can be enabled by setting bit 2

                                   ||       || when writing to msr 0x4b564d02

------------------------------------------------------------------------------

KVM_FEATURE_CLOCKSOURCE_STABLE_BIT ||    24 || host will warn if no guest-side

                                   ||       || per-cpu warps are expected in

                                   ||       || kvmclock.

Documentation/virtual/kvm/msr.txt

+2 −1
Original line number Diff line number Diff line
@@ -170,7 +170,8 @@ MSR_KVM_ASYNC_PF_EN: 0x4b564d02 
	when asynchronous page faults are enabled on the vcpu 0 when

	disabled. Bit 1 is 1 if asynchronous page faults can be injected

	when vcpu is in cpl == 0. Bit 2 is 1 if asynchronous page faults

	are delivered to L1 as #PF vmexits.

	are delivered to L1 as #PF vmexits.  Bit 2 can be set only if

	KVM_FEATURE_ASYNC_PF_VMEXIT is present in CPUID.



	First 4 byte of 64 byte memory location will be written to by

	the hypervisor at the time of asynchronous page fault (APF)

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 14

SUBLEVEL = 25

SUBLEVEL = 26

EXTRAVERSION =

NAME = Petit Gorille

arch/arm64/net/bpf_jit_comp.c

+3 −2
Original line number Diff line number Diff line
@@ -238,8 +238,9 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx) 
	off = offsetof(struct bpf_array, map.max_entries);

	emit_a64_mov_i64(tmp, off, ctx);

	emit(A64_LDR32(tmp, r2, tmp), ctx);

	emit(A64_MOV(0, r3, r3), ctx);

	emit(A64_CMP(0, r3, tmp), ctx);

	emit(A64_B_(A64_COND_GE, jmp_offset), ctx);

	emit(A64_B_(A64_COND_CS, jmp_offset), ctx);



	/* if (tail_call_cnt > MAX_TAIL_CALL_CNT)

	 *     goto out;
@@ -247,7 +248,7 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx) 
	 */

	emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx);

	emit(A64_CMP(1, tcc, tmp), ctx);

	emit(A64_B_(A64_COND_GT, jmp_offset), ctx);

	emit(A64_B_(A64_COND_HI, jmp_offset), ctx);

	emit(A64_ADD_I(1, tcc, tcc, 1), ctx);



	/* prog = array->ptrs[index];

arch/powerpc/net/bpf_jit_comp64.c

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ static void bpf_jit_emit_tail_call(u32 *image, struct codegen_context *ctx, u32 
	 *   goto out;

	 */

	PPC_LWZ(b2p[TMP_REG_1], b2p_bpf_array, offsetof(struct bpf_array, map.max_entries));

	PPC_RLWINM(b2p_index, b2p_index, 0, 0, 31);

	PPC_CMPLW(b2p_index, b2p[TMP_REG_1]);

	PPC_BCC(COND_GE, out);