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Commit 4534459f authored by Narender Ankam's avatar Narender Ankam
Browse files

clk: qcom: mdss: add support for DSI 28LPM PLL 



Add upstream support to program the DSI 28LPM PLL
to drive DSI byte and pxl clks.

Change-Id: I08e7b49cce7f30094b619374f5e4cf186397c4cc
Signed-off-by: default avatarNarender Ankam <nankam@codeaurora.org>
parent c426bc6f

Documentation/devicetree/bindings/fb/mdss-pll.txt

+16 −12
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Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI



mdss-pll is a pll controller device which supports pll devices that are

compatiable with MIPI display serial interface specification, HDMI and edp.

mdss-pll is a pll controller device which supports pll devices that

are compatible with MIPI display serial interface specification,

HDMI and edp.



Required properties:

- compatible:		Compatible name used in the driver. Should be one of:
@@ -12,9 +13,12 @@ Required properties: 
                        "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",

                        "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",

                        "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",

			"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_dsi_pll_8952",

			"qcom,mdss_dsi_pll_8937", "qcom,mdss_hdmi_pll_8996_v3_1p8",

			"qcom,mdss_dsi_pll_8953"

                        "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",

                        "qcom,mdss_edp_pll_8996_v3",  "qcom,mdss_edp_pll_8996_v3_1p8",

                        "qcom,mdss_dsi_pll_10nm",  "qcom,mdss_dp_pll_8998",

                        "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",

                        "qcom,mdss_dsi_pll_7nm",   "qcom,mdss_dp_pll_7nm",

			"qcom,mdss_dsi_pll_28lpm"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/qcom/mdss/Makefile

+2 −0
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@@ -6,3 +6,5 @@ obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-10nm-util.o 
obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-7nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28lpm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28nm-util.o

drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c

+436 −181

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drivers/clk/qcom/mdss/mdss-dsi-pll-28nm-util.c

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drivers/clk/qcom/mdss/mdss-dsi-pll-28nm.h

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/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef __MDSS_DSI_PLL_28NM_H

#define __MDSS_DSI_PLL_28NM_H



#define DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG          (0x0020)

#define DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2       (0x0064)

#define DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG         (0x0068)

#define DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1         (0x0070)



#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG	(0x0004)

#define DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG	(0x0028)

#define DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG		(0x0010)



struct ssc_params {

	s32 kdiv;

	s64 triang_inc_7_0;

	s64 triang_inc_9_8;

	s64 triang_steps;

	s64 dc_offset;

	s64 freq_seed_7_0;

	s64 freq_seed_15_8;

};



struct mdss_dsi_vco_calc {

	s64 sdm_cfg0;

	s64 sdm_cfg1;

	s64 sdm_cfg2;

	s64 sdm_cfg3;

	s64 cal_cfg10;

	s64 cal_cfg11;

	s64 refclk_cfg;

	s64 gen_vco_clk;

	u32 lpfr_lut_res;

	struct ssc_params ssc;

};



unsigned long vco_28nm_recalc_rate(struct clk_hw *hw,

				unsigned long parent_rate);

int vco_28nm_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate);

long vco_28nm_round_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long *parent_rate);

int vco_28nm_prepare(struct clk_hw *hw);

void vco_28nm_unprepare(struct clk_hw *hw);



int analog_postdiv_reg_write(void *context,

				unsigned int reg, unsigned int div);

int analog_postdiv_reg_read(void *context,

				unsigned int reg, unsigned int *div);

int byteclk_mux_write_sel(void *context,

				unsigned int reg, unsigned int val);

int byteclk_mux_read_sel(void *context,

				unsigned int reg, unsigned int *val);

int pixel_clk_set_div(void *context,

				unsigned int reg, unsigned int div);

int pixel_clk_get_div(void *context,

				unsigned int reg, unsigned int *div);



int dsi_pll_lock_status(struct mdss_pll_resources *rsc);

#endif /* __MDSS_DSI_PLL_28NM_H */