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Commit 44f40751 authored by Jayadev K's avatar Jayadev K Committed by Gerrit - the friendly Code Review server
Browse files

clk: qcom: gcc: Add clocks for hsi2s driver 



The hsi2s driver needs lpass_sdr functional group clock
support. Adding these entries to the gcc clock driver as
protected clocks. The protected property is deleted for
auto platform.

Change-Id: I84e76dcb3348920120de960c780e31192f29fb6e
Signed-off-by: default avatarJayadev K <jayak@codeaurora.org>
parent b07e0179

arch/arm64/boot/dts/qcom/sa6155.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 


&clock_gcc {

	compatible = "qcom,gcc-sa6155", "syscon";

	/delete-property/ protected-clocks;

};



&clock_videocc {

arch/arm64/boot/dts/qcom/sa6155p.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ 


&clock_gcc {

	compatible = "qcom,gcc-sa6155", "syscon";

	/delete-property/ protected-clocks;

};



&clock_videocc {

arch/arm64/boot/dts/qcom/sm6150.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -822,6 +822,13 @@ 
		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		protected-clocks = <GCC_SDR_CORE_CLK>,

				<GCC_SDR_WR0_MEM_CLK>,

				<GCC_SDR_WR1_MEM_CLK>,

				<GCC_SDR_WR2_MEM_CLK>,

				<GCC_SDR_CSR_HCLK>,

				<GCC_SDR_PRI_MI2S_CLK>,

				<GCC_SDR_SEC_MI2S_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

drivers/clk/qcom/gcc-sm6150.c

+98 −0
Original line number Diff line number Diff line
@@ -3243,6 +3243,97 @@ static struct clk_branch gcc_usb2_sec_clkref_clk = { 
	},

};



static struct clk_branch gcc_sdr_core_clk = {

	.halt_reg = 0x46004,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46004,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_core_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_wr0_mem_clk = {

	.halt_reg = 0x46008,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46008,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_wr0_mem_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_wr1_mem_clk = {

	.halt_reg = 0x46010,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46010,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_wr1_mem_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_wr2_mem_clk = {

	.halt_reg = 0x46018,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_wr2_mem_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_csr_hclk = {

	.halt_reg = 0x46020,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46020,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_csr_hclk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_pri_mi2s_clk = {

	.halt_reg = 0x46024,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46024,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_pri_mi2s_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_sdr_sec_mi2s_clk = {

	.halt_reg = 0x46028,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x46028,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdr_sec_mi2s_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



/* Measure-only clock for ddrss_gcc_debug_clk. */

static struct clk_dummy measure_only_mccc_clk = {

	.rrate = 1000,
@@ -3465,6 +3556,13 @@ static struct clk_regmap *gcc_sm6150_clocks[] = { 
	[GCC_RX3_USB2_CLKREF_CLK] = &gcc_rx3_usb2_clkref_clk.clkr,

	[GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr,

	[GCC_USB2_SEC_CLKREF_CLK] = &gcc_usb2_sec_clkref_clk.clkr,

	[GCC_SDR_CORE_CLK] = &gcc_sdr_core_clk.clkr,

	[GCC_SDR_WR0_MEM_CLK] = &gcc_sdr_wr0_mem_clk.clkr,

	[GCC_SDR_WR1_MEM_CLK] = &gcc_sdr_wr1_mem_clk.clkr,

	[GCC_SDR_WR2_MEM_CLK] = &gcc_sdr_wr2_mem_clk.clkr,

	[GCC_SDR_CSR_HCLK] = &gcc_sdr_csr_hclk.clkr,

	[GCC_SDR_PRI_MI2S_CLK] = &gcc_sdr_pri_mi2s_clk.clkr,

	[GCC_SDR_SEC_MI2S_CLK] = &gcc_sdr_sec_mi2s_clk.clkr,

};



static const struct qcom_reset_map gcc_sm6150_resets[] = {

include/dt-bindings/clock/qcom,gcc-sm6150.h

+7 −0
Original line number Diff line number Diff line
@@ -193,6 +193,13 @@ 
#define GCC_USB2_PRIM_CLKREF_CLK		173

#define GCC_USB2_SEC_CLKREF_CLK			174

#define GCC_RX3_USB2_CLKREF_CLK			175

#define GCC_SDR_CORE_CLK			176

#define GCC_SDR_WR0_MEM_CLK			177

#define GCC_SDR_WR1_MEM_CLK			178

#define GCC_SDR_WR2_MEM_CLK			179

#define GCC_SDR_CSR_HCLK			180

#define GCC_SDR_PRI_MI2S_CLK			181

#define GCC_SDR_SEC_MI2S_CLK			182



/* GCC Resets */

#define GCC_QUSB2PHY_PRIM_BCR			0